RAM with dual precharge circuit and write recovery circuitry

Claim 1

A memory having a read mode and a write mode, comprising: an array of memory cells coupled to bit line pairs and word lines at intersections thereof; a pair of data lines; output means, coupled to the pair of data lines, for providing an output signal representative of a logic state present on the data lines when the memory is in the read mode; input means, coupled to the pair of data lines, for driving the pair of data lines to a logic state representative of a logic state of an input signal when the input means is enabled by a write enable pulse; first precharge means, coupled to the data lines, for precharging the data lines in response to a data transition pulse; generator means, coupled to the input means, for providing the write enable pulse in response to the memory making a transition from the read mode to the write mode, providing the write enable pulse in response to a change in logic state of the input signal when the memory is in the write mode, and providing the data transition pulse in response to the memory making a transition from the write mode to the read mode during the write enable pulse, said data transition pulse delayed in time from said write enable pulse; column decoder means, coupled to the bit line pairs, for coupling a selected bit line pair to the pair of data lines as determined by a column address; and row decoder means, coupled to the work lines, for enabling a selected word line as determined by a row address.