US4722074A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor storage unit with I/O bus precharging and equalization
Assignee: Mitsubishi Electric Corp
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Filing: 1985-09-10
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Granted: 1988-01-26
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Expires: 2005-09-10
Abstract
Abstract A first precharging and equalizing circuit (7) precharges and equalizes I/O buses (10 and 10') in advance to selection of bit lines, and following thereto, a second precharging and equalizing circuit (12) precharges and equalizes the I/O buses (10 and 10') during driving operation of a sense amplifier (2). Thus, potential levels of the I/O Buses (10 and 10') are prevented from being changed by vibration of the output level of the sense amplifier (2) transmitted to the I/O buses (10 and 10') through parasitic capacitance (8) during driving operation of the sense amplifier (2).
Inventors
- 👤 Kazuyasu Fujishima
- 👤 Masaki Kumanoya
- 👤 Hideshi Miyatake
- 👤 Hideto Hidaka
- 👤 Katsumi Dosaka
- 👤 Tsutomu Yoshihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
137 words
A semiconductor storage unit comprising: a plurality of memory cells arranged in the form of a matrix along directions of rows and columns; a plurality of word lines commonly connected with every row of said memory cells; a plurality of bit lines commonly connected with every column of said memory cells; sense amplifers for detecting and amplifying cell information transmitted from said memory cells to said bit lines in response to selection of said word lines; I/O buses connected to selected ones of said bit lines in response to selection of said bit lines; first precharge means for precharging said I/O buses by the supply voltage prior to said selection of said bit lines; and second precharge means for precharging said holding potentials of said I/O buses for supply voltage during driving operation of said sense amplifiers.
Claim 2
Dependent Claim
137 words
A semiconductor storage unit comprising: a plurality of memory cells arranged in the form of a matrix along directions of rows and columns; a plurality of word lines commonly connected with every row of said memory cells; a plurality of bit lines commonly connected with every column of said memory cells; sense amplifers for detecting and amplifying cell information transmitted from said memory cells to said bit lines in response to selection of said word lines; I/O buses connected to selected ones of said bit lines in response to selection of said bit lines; first precharge means for precharging said I/O buses by the supply voltage prior to said selection of said bit lines; and second precharge means for precharging said holding potentials of said I/O buses for supply voltage during driving operation of said sense amplifiers.
Claim 3
Dependent Claim
20 words
A semiconductor storage unit in accordance with claim 1, wherein said memory cells are single-transistor type MOS dynamic memory cells.
Claim 4
Dependent Claim
36 words
A semiconductor storage unit in accordance with claim 1, wherein said second precharge means precharges said I/O buses for a prescribed period of time from the leading edge of a driving signal for said sense amplifiers.
Claim 5
Dependent Claim
116 words
A semiconductor unit in accordance with claim 3, wherein said second precharge means includes: a timing signal producing circuit for producing a first timing signal which rises in response to an address strobe signal for said word lines and falls in response to a delayed signal of said driving signal for said sense amplifiers and a second timing signal which rises in response to said driving signal for said sense amplifiers and falls in response to said delayed signal of said driving signal for said sense amplifiers, and a precharge circuit for precharging said I/O buses when both of said first and second timing signal produced by said timing signal producing circuit are at high levels.
Claim 6
Dependent Claim
49 words
A semiconductor unit in accordance with claim 4, wherein said first precharge means and said second precharge means are commonly used at a portion corresponding to said precharge circuit, said precharge circuit receiving signals for determining selection timing of said bit lines and said first and second timing signals.
Claim 7
Dependent Claim
35 words
A semiconductor storage unit in accordance with claim 1, wherein said semiconductor storage unit is in an open bit line system in which said bit lines are connected to both sides of said sense amplifiers.
References Cited (Backward Citations)
US4125878A
Cited
US4138740A
Cited
US4417329A
Cited
US4475178A
Cited
US4458337A
Cited
US4503522A
Cited
JPS57195387A
Cited
JPS5819793A
Cited
JPS58182190A
Cited
US4449207A
Cited
JPS59203298A
Cited
JPS6085492A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |