Semiconductor memory device having divided regular circuits

Claim 2

A semiconductor memory device having a periphery, comprising: a plurality of word lines; a plurality of bit lines; at least two separated regular pattern circuit areas, each comprising first elements operatively connected to and arranged regularly in line with at least one of said word lines and said bit lines; an irregular circuit area, arranged between said separated regular pattern circuit areas, said irregular circuit area comprising second elements operatively connected to said regular pattern circuit areas and irregularly arranged with respect to the one of said word lines and said bit lines; and bonding pad areas, operatively connected to said irregular circuit area, arranged on the periphery of said device.

Claim 3

A device as set forth in claim 1, wherein said bonding pad areas comprise first pads, operatively connected to said irregular circuit area and arranged outside of said separated regular pattern circuit areas on the periphery of said device.

Claim 4

A device as set forth in claim 2, wherein said bonding pad areas further comprise second pads, operatively connected to said irregular circuit area and arranged outside of said irregular circuit area on the periphery of said device.

Claim 5

A device as set forth in claim 3, wherein each of said second pads, arranged outside of said irregular circuit area, is provided to transfer a signal which may be an unvarying potential used in powering said device, and wherein corresponding pads, included in said first pads arranged outside said separated regular pattern circuit areas, each transfers a signal substantially identical to the signal transferred by a corresponding one of the second pads.

Claim 6

A device as set forth in claim 4, further comprising electrically connecting means, operatively connected to said irregular circuit area and to each of said second and corresponding first pads, respectively, for connecting said second and corresponding pads, transferring substantially identical signals, to each other.

Claim 7

A device as set forth in claim 5, wherein said electrically connecting means comprises connections operatively connected to said irregular circuit area and said second and corresponding first pads transferring substantially identical signals.

Claim 8

A device as set forth in claim 5, wherein said electrically connecting means comprises gates operatively connected in parallel, each of said gates being operatively connected to one of said second and corresponding pads.

Claim 9

A device as set forth in claim 7, wherein each of said second and corresponding first pads have a potential, and further comprising preventing means, each of said preventing means operatively connected to ground and one of said second and corresponding first pads transferring substantially identical signals, for preventing the potential of the one of said second and corresponding first pads from being in a floating state.

Claim 10

A device as set forth in claim 8, further comprising means, operatively connected to said preventing means, for selecting and operating only one of said preventing means in each pair of said second and corresponding first pads.

Claim 11

A semiconductor memory device on a semiconductor chip having first and second edges, a third edge opposite from the first edge, and a fourth edge between the first and third edge and opposite from the second edge, said device including word lines and bit lines and comprising: a first regular pattern circuit area, located closer to the first edge than the third edge, having formed therein first circuit elements operatively connected to the word and bit lines and arranged in a regular pattern with respect to at least one of the word and bit lines; a second regular pattern circuit area, located closer to the third edge than the first edge, having formed therein second circuit elements operatively connected to the word and bit lines and arranged in a regular pattern with respect to the one of the word and bit lines; and an irregular circuit area, located between said first and second regular pattern circuit areas, having formed therein third circuit elements irregularly arranged with respect to the one of the word and bit lines.

Claim 12

A semiconductor memory device on a semiconductor chip having first and second edges, a third edge opposite from the first edge, and a fourth edge between the first and third edge and opposite from the second edge, said device including word lines and bit lines and comprising: a first regular pattern circuit area, located closer to the first edge than the third edge, having formed therein first circuit elements operatively connected to the word and bit lines and arranged in a regular pattern with respect to at least one of the word and bit lines; a second regular pattern circuit area, located closer to the third edge than the first edge, having formed therein second circuit elements operatively connected to the word and bit lines and arranged in a regular pattern with respect to the one of the word and bit lines; and an irregular circuit area, located between said first and second regular pattern circuit areas, having formed therein third circuit elements irregularly arranged with respect to the one of the word and bit lines.

Claim 13

A semiconductor memory device as set forth in claim 10, wherein said device includes bonding posts and further comprises: a first bonding pad area, located between said first regular pattern circuit area and the first edge of the chip, having formed therein first bonding pad means, operatively connected to the third circuit elements in said irregular circuit area, for connecting the chip to the bonding posts of said device, and a second bonding pad area, located between said second regular pattern circuit area and the third edge of the chip, having formed therein second bonding pad means, operatively connected the third circuit elements in said irregular circuit area, for connecting the chip to the bonding posts of said device.

Claim 14

A semiconductor memory device as set forth in claim 11, further comprising: a third bonding pad area, located between said irregular pattern area and the second edge of the chip, having formed therein third bonding pad means, operatively connected to the third circuit elements in said irregular circuit area, for connecting the chip to the bonding posts of said device; and a fourth bonding pad area, located between said irregular circuit area and the fourth edge of the chip, having formed therein bonding pad means, operatively connected to the third circuit elements in said irregular circuit area, for connecting the chip to the bonding posts of said device.

Claim 15

A semiconductor memory device as set forth in claim 12, wherein said first, second, third and fourth bonding pad means each comprises bonding pads, operatively connected to the third circuit elements in said irregular circuit area, and wherein at least some of the bonding pads in said third and fourth bonding pad areas include alternative bonding pads which provide functions that are identical to corresponding bonding pads in said first and second bonding pad areas.

Claim 16

A device as set forth in claim 1, wherein said irregular circuit area comprises peripheral circuits operatively connected to said separated regular pattern circuit areas and said bonding pad areas.

Claim 17

A device as set forth in claim 14, wherein said peripheral circuits comprise input/output circuits operatively connected to said separated regular pattern circuit areas and said bonding pad areas.

Claim 18

A semiconductor memory device as set forth in claim 10, wherein said irregular circuit area comprises peripheral circuits operatively connected to at least one of the word and bit lines.

Claim 19

A semiconductor memory device as set forth in claim 16, wherein said peripheral circuits comprises input/output circuits operatively connected to at least one of the word and bit lines.