US4712192A
Expired / Lapsed
US
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Semiconductor memory device and fabrication process thereof
Assignee: Hitachi Ltd
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Filing: 1985-10-04
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Granted: 1987-12-08
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Expires: 2005-10-04
Abstract
Abstract Herein disclosed is a semiconductor memory device which is composed of a peripheral circuit unit equipped with a gate protection circuit having a protection resistor and a memory cell unit so that it can be used as an MISFET type static RAM and which is characterized in that the protection resistor is made of a polycrystalline silicon film having substantially the same resistivity as that of an overlying polycrystalline silicon film formed to merge into the load resistor of the memory cell unit.
Inventors
- 👤 Nobuyoshi Tanimura
- 👤 Tokumasa Yasui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:53
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10D88/00; H10D89/00; H10D89/60; H10D89/601; H10D89/911; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
239 words
A semiconductor memory device having MIS transistors composing memory cells, the memory cells having load devices, the load devices being connected to a power supply line, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuit being connected, through a protection resistor, with a bonding pad, the memory device being fabricated by a process including the steps of: forming a first film of an electrically conductive material, which serves as the gate of the MIS transistors composing memory cells of the semiconductor memory device, over a semiconductor material, said first film having a first resistivity; forming an insulation film to cover the semiconductor material which is formed with each of the MIS transistors composing said memory cells; and forming second films, which second films include a layer of polycrystalline silicon, which second films respectively serve as each load device of each of said memory cells, as a wiring for connecting the load device with a power supply line and as the protection resistor through which the gate of at least one of the MIS transistors composing peripheral circuits is connected with the bonding pad, over said insulation film covering said semiconductor material, the resistivity of the second films serving as said protection resistor and as said wiring being lower than that of the second film serving as said load device and higher than that of said first film.
Claim 2
Dependent Claim
239 words
A semiconductor memory device having MIS transistors composing memory cells, the memory cells having load devices, the load devices being connected to a power supply line, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuit being connected, through a protection resistor, with a bonding pad, the memory device being fabricated by a process including the steps of: forming a first film of an electrically conductive material, which serves as the gate of the MIS transistors composing memory cells of the semiconductor memory device, over a semiconductor material, said first film having a first resistivity; forming an insulation film to cover the semiconductor material which is formed with each of the MIS transistors composing said memory cells; and forming second films, which second films include a layer of polycrystalline silicon, which second films respectively serve as each load device of each of said memory cells, as a wiring for connecting the load device with a power supply line and as the protection resistor through which the gate of at least one of the MIS transistors composing peripheral circuits is connected with the bonding pad, over said insulation film covering said semiconductor material, the resistivity of the second films serving as said protection resistor and as said wiring being lower than that of the second film serving as said load device and higher than that of said first film.
Claim 3
Dependent Claim
128 words
A semiconductor memory device according to claim 1, wherein the second films are films formed by processing steps including depositing polycrystalline silicon at the locations of each load device of the memory cells, at the location of the wiring for connecting the load devices with a power supply line, and at the location of the protection resistor; masking the polycrystalline silicon at the location of each load device; and introducing impurity ions into the polycrystalline silicon at the location of the wiring and protection resistor to lower the resistivity thereof, said impurity ions being introduced into the polycrystalline silicon in an amount such that the resistivity thereof is lower than that of the polycrystalline silicon serving as the load device but higher than that of the first film.
Claim 4
Dependent Claim
175 words
A semiconductor memory device according to claim 1, wherein said protection resistor is in electrical contact with a protection diode formed in the semiconductor material, said protection diode being formed by a process including the steps of: introducing impurity ions of a first conductivity type, opposite to that of the semiconductor material, into the semiconductor material at the location at which the protection resistor is to be formed to contact the semiconductor material, to form a first semiconductor region, of conductivity type opposite to that of the semiconductor material, in the semiconductor material at the location at which the protection resistor is formed to contact the semiconductor material; and introducing impurity ions of conductivity type opposite to said first conductivity type into said first semiconductor region, to form a second semiconductor region in the first semiconductor region, of conductivity type opposite to the conductivity type of the first semiconductor region; and wherein the protection resistor means is formed in contact with the second semiconductor region, the first and second semiconductor regions forming said protection diode.
Claim 5
Dependent Claim
168 words
A static random access memory device having MIS transistors composing memory cells, the memory cells having load devices, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuits being connected through a protection resistor means with a bonding pad, the static random access memory device being fabricated by a process comprising the steps of: forming a first level conductive film over a semiconductor material, said first level conductive film forming the gate electrodes of the MIS transistors of the memory cells; forming an insulator film over said semiconductor material; and forming second level conductive films over said semiconductor material, said second level conductive films including a polycrystalline silicon layer, said second level conductive films being formed simultaneously at the location of said load devices and at the location of said protection resistor means, whereby said second level conductive films to form said load devices and at least a part of said protection resistor means are simultaneously provided.
Claim 6
Dependent Claim
168 words
A static random access memory device having MIS transistors composing memory cells, the memory cells having load devices, and peripheral circuits having MIS transistors, with the gate of at least one of the MIS transistors of the peripheral circuits being connected through a protection resistor means with a bonding pad, the static random access memory device being fabricated by a process comprising the steps of: forming a first level conductive film over a semiconductor material, said first level conductive film forming the gate electrodes of the MIS transistors of the memory cells; forming an insulator film over said semiconductor material; and forming second level conductive films over said semiconductor material, said second level conductive films including a polycrystalline silicon layer, said second level conductive films being formed simultaneously at the location of said load devices and at the location of said protection resistor means, whereby said second level conductive films to form said load devices and at least a part of said protection resistor means are simultaneously provided.
Claim 7
Dependent Claim
89 words
A static random access memory device according to claim 4, wherein said first level conductive film is a film formed to have a first resistivity and said second level conductive films are films formed to have a second resistivity, and wherein impurity ions are doped into the polycrystalline silicon layer of said second level conductive films at the location of said protection resistor means to lower the resistivity thereof, to thereby form protection resistor means having a resistivity greater than said first resistivity but less than said second resistivity.
Claim 8
Dependent Claim
204 words
A semiconductor memory device comprising: an array of memory cells constituted by a semiconductor integrated circuit formed using a semiconductor material and composed of MISFETs, each of said memory cells including a pair of driver MISFETs formed at one face of said semiconductor material, a pair of load devices connected in series with said paired driver MISFETs, respectively, first conductive means for connecting each of said load devices with a power supply line, and second conductive means for cross-coupling the gate of one of said MISFETs to the drain of the other MISFET; and peripheral circuits formed in said semiconductor material in relation to said array of memory cells and composed of MISFETs, an electrode of at least one of said MISFETs composing said peripheral circuits being connected through a protection resistor with a bonding pad, wherein the improvements reside: in that upper and lower strips of conductive material are provided over the semiconductor material, in that each of the load devices of each of said memory cells and said protection resistor are made of said upper strip of conductive material; and in that said MISFETs of each of said memory cells and peripheral circuits are made of said lower strips of conductive material.
Claim 9
Dependent Claim
204 words
A semiconductor memory device comprising: an array of memory cells constituted by a semiconductor integrated circuit formed using a semiconductor material and composed of MISFETs, each of said memory cells including a pair of driver MISFETs formed at one face of said semiconductor material, a pair of load devices connected in series with said paired driver MISFETs, respectively, first conductive means for connecting each of said load devices with a power supply line, and second conductive means for cross-coupling the gate of one of said MISFETs to the drain of the other MISFET; and peripheral circuits formed in said semiconductor material in relation to said array of memory cells and composed of MISFETs, an electrode of at least one of said MISFETs composing said peripheral circuits being connected through a protection resistor with a bonding pad, wherein the improvements reside: in that upper and lower strips of conductive material are provided over the semiconductor material, in that each of the load devices of each of said memory cells and said protection resistor are made of said upper strip of conductive material; and in that said MISFETs of each of said memory cells and peripheral circuits are made of said lower strips of conductive material.
Claim 10
Dependent Claim
48 words
A semiconductor memory device according to claim 6, wherein the upper strip includes first and second portions each having a different sheet resistance, respectively forming the load devices and the protection resistor, and wherein the upper strip has a greater sheet resistance than that of the lower strip.
Claim 11
Dependent Claim
31 words
A semiconductor memory device according to claim 6, wherein said lower strip of conductive material includes refractory metal or silicide thereof, and the upper strip of conductive material is polycrystalline silicon.
Claim 12
Dependent Claim
68 words
A semiconductor memory device according to claim 8, further including word lines for connecting the memory cells, said word lines serving in part as the gate electrodes of the MIS transistors of the memory cells, the word lines being formed of refractory metal or a silicide thereof, whereby the gate electrodes of the MIS transistors of the memory cells are formed of the refractory metal or silicide thereof.
Claim 13
Dependent Claim
19 words
A semiconductor memory device according to claim 9, wherein the memory device is a static random access memory device.
Claim 14
Dependent Claim
36 words
A semiconductor memory device according to claim 6, wherein said load devices and said first conductive means of each memory cell and said power supply line are integrally formed from said upper strip of conductive material.
Claim 15
Dependent Claim
18 words
A semiconductor memory device according to claim 11, wherein said upper strip of conductive material is polycrystalline silicon.
Claim 16
Dependent Claim
22 words
A semiconductor memory device according to claim 12, wherein said lower strip of conductive material includes refractory metal or a silicide thereof.
Claim 17
Dependent Claim
68 words
A semiconductor memory device according to claim 13, further including word lines for connecting the memory cells, said word lines serving in part as the gate electrodes of the MIS transistors of the memory cells, the word lines being formed of refractory metal or a silicide thereof, whereby the gate electrodes of the MIS transistors of the memory cells are formed of the refractory metal or silicide thereof.
Claim 18
Dependent Claim
96 words
A semiconductor integrated circuit device, comprising at least one MISFET, other circuit elements and at least one pad, said other circuit elements including at least one protection resistor, each of the at least one MISFET having a gate electrode, and said electrode and pad are electrically connected by said protection resistor, wherein the gate electrodes of the at least one MISFET are formed from a first level conductive material layer which includes refractory metal or a silicide thereof, and wherein said protection resistor is formed from a second level conductive material layer which includes polycrystalline silicon.
Claim 19
Dependent Claim
96 words
A semiconductor integrated circuit device, comprising at least one MISFET, other circuit elements and at least one pad, said other circuit elements including at least one protection resistor, each of the at least one MISFET having a gate electrode, and said electrode and pad are electrically connected by said protection resistor, wherein the gate electrodes of the at least one MISFET are formed from a first level conductive material layer which includes refractory metal or a silicide thereof, and wherein said protection resistor is formed from a second level conductive material layer which includes polycrystalline silicon.
Claim 20
Dependent Claim
73 words
A semiconductor integrated circuit device, comprising at least one MISFET, and other circuit elements, said other circuit elements including at least one protection resistor, each of the at least one MISFET having a gate electrode, wherein the gate electrodes of the at least one MISFET are formed from a first level conductive material layer, and wherein the other circuit elements, including the protection resistor, are formed from a second level conductive material layer.
Claim 21
Dependent Claim
73 words
A semiconductor integrated circuit device, comprising at least one MISFET, and other circuit elements, said other circuit elements including at least one protection resistor, each of the at least one MISFET having a gate electrode, wherein the gate electrodes of the at least one MISFET are formed from a first level conductive material layer, and wherein the other circuit elements, including the protection resistor, are formed from a second level conductive material layer.
Claim 22
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 16, wherein the second level conductive material layer is made of polycrystalline silicon.
Claim 23
Dependent Claim
31 words
A static random access memory device according to claim 4, wherein said first film is a film formed by depositing a metal having a high melting point, or a silicide thereof.
Claim 24
Dependent Claim
182 words
A static random access memory device according to claim 4, wherein said protection resistor means is in electrical contact with a protection diode formed in the semiconductor material, said protection diode being formed by a process including the steps of: introducing impurity ions of a first conductivity type, opposite to that of the semiconductor material, into the semiconductor material at the location at which the protection resistor means is to be formed to contact the semiconductor material, to form a first semiconductor region, of conductivity type opposite to that of the semiconductor material, in the semiconductor material at the location at which the protection resistor means is to be formed to contact the semiconductor material; and introducing impurity ions of conductivity type opposite to said first conductivity type into said first semiconductor region, to form a second semiconductor region, in the first semiconductor region, of conductivity type opposite to the conductivity type of the first semiconductor region; and wherein the protection resistor means is formed in contact with the second semiconductor region, the first and second semiconductor region forming said protection diode.
References Cited (Backward Citations)
US4651409A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-07 | 1991-06-08 | 1991-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-07 | 1995-06-08 | 1995-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-07 | 1999-06-08 | 1999-12-08 | $7700.00 | Window Closed / Lapsed |