Multiplying circuit with improved linearity and reduced leakage

Claim 2

A multiplying circuit comprising: first and second differential amplifiers for receiving a first input signal and each having first and second output terminals and a common emitter terminal, the first output terminal of said first differential amplifier being connected to the second output terminal of said second differential amplifier, and the second output terminal of said first differential amplifier being connected to the first output terminal of said second differential amplifier; load means connected to said first and second output terminals of said first and second differential amplifiers; first and second common-base transistors having bases tied to a constant potential and collectors respectively connected to said common emitter terminals of said first and second differential amplifiers; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a predetermined DC offset and third and fourth output terminals, and said emitters of said first and second common-base transistors being connected only to said third and fourth output terminals of said third differential amplifiers, respectively, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 3

A multiplying circuit according to claim 1, wherein each of said third differential amplifiers comprises a pair of transistors each having an emitter, and each of said third differential amplifiers has a predetermined emitter area ratio between the emitters of the transistors used therein to acquire said predetermined DC offset.

Claim 4

A multiplying circuit according to claim 1, wherein said first and second common-base transistors each have an emitter area smaller than the emitter area of one or more of the transistors used in each of said third differential amplifiers.

Claim 5

A multiplying circuit according to claim 1, wherein one of said third differential amplifiers is constituted by a pair of transistors having an emitter area ratio of 4:1 between emitters thereof, and another is constituted by a pair of transistors having an emitter area ratio of 1:4 between emitters thereof.

Claim 6

A multiplying circuit according to claim 1, wherein said third differential amplifiers are constituted by three pairs of transistors, a first one having an emitter area ratio of 8:1, a second one 1:1, and a third one 1:8.

Claim 7

A multiplying circuit according to claim 1, wherein said third differential amplifiers are constituted by four pairs of transistors, a first one having an emitter area ratio of 13:1, a second one 2:1, a third one 1:2, and a fourth one 1:13.

Claim 8

A multiplying circuit according to claim 1, wherein said bases of said first and second common-base transistors are tied to a ground potential as the constant potential.

Claim 9

A multiplying circuit comprising: a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers; load means connected to said first and second output terminals of said first and second differential amplifiers; a plurality of first common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said first differential amplifiers, and emitters commonly connected; a plurality of second common-base transistors having bases also tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said second differential amplifiers, and emitters commonly connected; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a predetermined DC offset and third and fourth output terminals and said common emitter terminals of said first and second common-base transistors being connected only to the third and fourth output terminals of each of said third differential amplifiers, respectively, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 10

A multiplying circuit comprising: a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers; load means connected to said first and second output terminals of said first and second differential amplifiers; a plurality of first common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said first differential amplifiers, and emitters commonly connected; a plurality of second common-base transistors having bases also tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said second differential amplifiers, and emitters commonly connected; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a predetermined DC offset and third and fourth output terminals and said common emitter terminals of said first and second common-base transistors being connected only to the third and fourth output terminals of each of said third differential amplifiers, respectively, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 11

A multiplying circuit according to claim 8, wherein each of said first, second and third differential amplifiers comprises at least one pair of transistors each having an emitter, and wherein said first to third differential amplifiers each have a predetermined emitter area ratio between the emitters of said transistors thereof to acquire said predetermined DC offset, and each of said first and second common-base transistors has a smaller emitter area than the emitter area of said pair of transistors constituting each of said third differential amplifiers.

Claim 12

A multiplying circuit according to claim 8, wherein said bases of said first and second common-base transistors are tied to a ground potential as the constant potential.

Claim 13

A multiplying circuit comprising: a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers; load means connected to said first and second output terminals of said first and second differential amplifiers; a plurality of first common-base transistors having bases tied to a constant potential, collectors connected to said common emitter terminals of said first differential amplifiers, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio; a plurality of second common-base transistors, having bases tied to a constant potential, collectors connected to said common emitter terminals of said second differential amplifiers, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a pair of output terminals, said common emitter terminals of said first and second common-base transistors being connected only to respective output terminals of each of said third differential amplifiers, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 14

A multiplying circuit comprising: a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers; load means connected to said first and second output terminals of said first and second differential amplifiers; a plurality of first common-base transistors having bases tied to a constant potential, collectors connected to said common emitter terminals of said first differential amplifiers, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio; a plurality of second common-base transistors, having bases tied to a constant potential, collectors connected to said common emitter terminals of said second differential amplifiers, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a pair of output terminals, said common emitter terminals of said first and second common-base transistors being connected only to respective output terminals of each of said third differential amplifiers, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 15

A multiplying circuit according to claim 11, wherein each of said first, second and third differential amplifiers comprises a pair of transistors having emitters, between which is set a predetermined emitter area ratio to acquire said respective predetermined DC offsets.

Claim 16

A multiplying circuit according to claim 11, wherein said bases of said first and second common-base transistors are tied to a ground potential as the constant potential.

Claim 17

A multiplying circuit comprising: a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers; load means connected to said first and second output terminals of said first and second differential amplifiers; a plurality of first common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said first differential amplifiers, and emitters; a plurality of second common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said second differential amplifiers, and emitters; a plurality of third common-base transistors having bases tied to a constant potential, collectors connected to emitters of said first common-base transistors, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio; a plurality of fourth common-base transistors having bases tied to a constant potential, collectors connected to emitters of said second common-base transistors, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have the predetermined emitter area ratio; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a pair of output terminals, said common emitter terminals of said third and fourth common-base transistors being connected only to respective output terminals of each of said third differential amplifiers, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 18

A multiplying circuit comprising: a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers; load means connected to said first and second output terminals of said first and second differential amplifiers; a plurality of first common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said first differential amplifiers, and emitters; a plurality of second common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said second differential amplifiers, and emitters; a plurality of third common-base transistors having bases tied to a constant potential, collectors connected to emitters of said first common-base transistors, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio; a plurality of fourth common-base transistors having bases tied to a constant potential, collectors connected to emitters of said second common-base transistors, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have the predetermined emitter area ratio; and a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a pair of output terminals, said common emitter terminals of said third and fourth common-base transistors being connected only to respective output terminals of each of said third differential amplifiers, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.

Claim 19

A multiplying circuit according to claim 14, wherein each of said first and second differential amplifiers comprises a pair of transistors having emitters, between which is set a predetermined emitter area ratio to acquire said respective predetermined DC offsets.

Claim 20

A multiplying circuit according to claim 14, wherein said first and second common-base transistors each have an emitter area smaller than the emitter area of said third and fourth common-base transistors.

Claim 21

A multiplying circuit according to claim 14, wherein said bases of said first to fourth common-base transistors are tied to a ground potential as the constant potential.

Claim 22

A multiplying circuit comprising: a differential amplifier for receiving a first input signal, having first and second output terminals and a common emitter terminal; a load circuit connected to at least one of said first and second output terminals of said differential amplifier; a common-emitter transistor having a base supplied with a second input signal; and a common-base transistor having a base tied to a constant potential, a collector connected only to said common emitter terminal of said differential amplifier, and an emitter connected only to a collector of said common-emitter transistor and having a smaller emitter area than said common-emitter transistor whereby an output signal proportional to the product of the first and second input signals appears at at least one of the first and second output terminals of said differential amplifier.

Claim 23

A multiplying circuit comprising: a differential amplifier for receiving a first input signal, having first and second output terminals and a common emitter terminal; a load circuit connected to at least one of said first and second output terminals of said differential amplifier; a common-emitter transistor having a base supplied with a second input signal; and a common-base transistor having a base tied to a constant potential, a collector connected only to said common emitter terminal of said differential amplifier, and an emitter connected only to a collector of said common-emitter transistor and having a smaller emitter area than said common-emitter transistor whereby an output signal proportional to the product of the first and second input signals appears at at least one of the first and second output terminals of said differential amplifier.

Claim 24

A multiplying circuit comprising: a plurality of differential amplifiers for receiving a first input signal, each of said differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, a load circuit connected to at least one of said first and second output terminals of each of said differential amplifiers; a common-emitter transistor having a base supplied with a second input signal and a plurality of common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said multiple differential amplifiers, respectively, and emitters connected only to a collector of said common-emitter transistor, said emitters of said common-base transistors being set to have a predetermined emitter area ratio.

Claim 25

A multiplying circuit comprising: a plurality of differential amplifiers for receiving a first input signal, each of said differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, a load circuit connected to at least one of said first and second output terminals of each of said differential amplifiers; a common-emitter transistor having a base supplied with a second input signal and a plurality of common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said multiple differential amplifiers, respectively, and emitters connected only to a collector of said common-emitter transistor, said emitters of said common-base transistors being set to have a predetermined emitter area ratio.

Claim 26

A multiplying circuit comprising: a plurality of differential amplifiers for receiving a first input signal, each of said differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, a load circuit connected to at least one output terminal of said first and second output terminals of each of said differential amplifiers; a common-emitter transistor having a base supplied with a second input signal; a plurality of first common-base transistors having bases tied to a constant potential, and emitters connected only to a collector of said common-emitter transistor, the emitters of said first common-base transistors being set to have a predetermined emitter area ratio; and a plurality of second common-base transistors having bases tied to a constant potential different from the constant potential applied to said first common-base transistors, collectors respectively connected to said common emitter terminals of said multiple differential amplifiers and emitters respectively connected to collectors of said first common-emitter transistors and having emitter areas equal to or smaller than a minimum emitter area of one of said first common-base transistors.

Claim 27

A multiplying circuit comprising: a plurality of differential amplifiers for receiving a first input signal, each of said differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, a load circuit connected to at least one output terminal of said first and second output terminals of each of said differential amplifiers; a common-emitter transistor having a base supplied with a second input signal; a plurality of first common-base transistors having bases tied to a constant potential, and emitters connected only to a collector of said common-emitter transistor, the emitters of said first common-base transistors being set to have a predetermined emitter area ratio; and a plurality of second common-base transistors having bases tied to a constant potential different from the constant potential applied to said first common-base transistors, collectors respectively connected to said common emitter terminals of said multiple differential amplifiers and emitters respectively connected to collectors of said first common-emitter transistors and having emitter areas equal to or smaller than a minimum emitter area of one of said first common-base transistors.

Claim 28

A multiplying circuit apparatus comprising: a plurality of multiplying circuits to which a plurality of first input signals are supplied respectively; and a common-emitter transistor commonly connected to said plurality of multiplying circuits and having a base to which a second input signal is supplied, each of said plurality of multiplying circuits comprising: a differential amplifier for receiving one of said first input signals, having first and second output terminals and a common emitter terminal; load means connected to said first and second output terminals; and a common-base transistor having a base tied to a constant potential and a collector connected only to said common emitter terminal of said differential amplifier, whereby an output signal proportional to the product of the first and second input signals is obtained from said multiplying circuits.

Claim 29

A multiplying circuit apparatus comprising: a plurality of multiplying circuits to which a plurality of first input signals are supplied respectively; and a common-emitter transistor commonly connected to said plurality of multiplying circuits and having a base to which a second input signal is supplied, each of said plurality of multiplying circuits comprising: a differential amplifier for receiving one of said first input signals, having first and second output terminals and a common emitter terminal; load means connected to said first and second output terminals; and a common-base transistor having a base tied to a constant potential and a collector connected only to said common emitter terminal of said differential amplifier, whereby an output signal proportional to the product of the first and second input signals is obtained from said multiplying circuits.