US5115409A
Expired / Lapsed
US
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Multiple-input four-quadrant multiplier
Assignee: Siemens AG
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Filing: 1989-08-14
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Granted: 1992-05-19
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Expires: 2009-08-14
Abstract
Abstract A four-quadrant multiplier based on a Gilbert cell is utilized to multiply several signals by a similar signal. The transistors in two pairs of coupled differential amplifiers of one input terminal of the inner multiplier that is activated like a Gilbert cell by way of a diode-and-transistor section have several emitters. Each pair of emitters in the right and the left branch of the miltiplier can be oppositely activated by way of a source of variable current or by way of a series of a transistor and a source of current. To process square-wave signals, the source of variable current is a source that can be engaged and disengaged by I 2 L gates.
Inventors
- 👤 Richard Stepp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:07
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163; G06J; G06J1/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
346 words
A four-quadrant multiplier in the form of a monolithic integrated electronic circuit, comprising: two signal-output terminals, one of which signal-output terminal consists of a first transistor with its collector connected to the collector of a third transistor and, via a first resistance, to a supply potential; and the other signal-output terminal consisting of a second transistor with its collector connected to the collector of a fourth transistor and, via a second resistance, to the supply potential; wherein the base of the first transistor is connected to the base of the fourth transistor, to the collector of a fifth transistor, and to the cathode of a first diode; and wherein the base of the second transistor is connected to the base of the third transistor, to the collector of a sixth transistor, and to the cathode of a second diode; wherein the anode of the first diode is connected, along with the anode of the second diode and via a third resistor, to the supply potential, wherein the emitters of the fifth transistor and of the sixth transistor are coupled to reference potential via a source of constant current, wherein the base of the sixth transistor comprises one of the multiplier's input terminals and the base of the fifth transistor comprises the other input terminal, wherein the first four transistors are multiple-emitter transistors, wherein each emitter of the first transistor is connected to one emitter of the second transistor and to the current-input terminal of a source of variable current, wherein the current-output terminal of the respective source of variable current is connected to reference potential, wherein the control-input terminal of each of said respective sources of variable current are non-inverting input terminals, such that each emitter of the third transistor is connected to a corresponding emitter of the fourth transistor and to the current-input terminal of an individual source of variable current, such that each current-output terminal of each of said respective sources of variable current is connected to reference potential, and wherein the control-input terminals of said sources of variable current are inverting input terminals.
Claim 2
Dependent Claim
346 words
A four-quadrant multiplier in the form of a monolithic integrated electronic circuit, comprising: two signal-output terminals, one of which signal-output terminal consists of a first transistor with its collector connected to the collector of a third transistor and, via a first resistance, to a supply potential; and the other signal-output terminal consisting of a second transistor with its collector connected to the collector of a fourth transistor and, via a second resistance, to the supply potential; wherein the base of the first transistor is connected to the base of the fourth transistor, to the collector of a fifth transistor, and to the cathode of a first diode; and wherein the base of the second transistor is connected to the base of the third transistor, to the collector of a sixth transistor, and to the cathode of a second diode; wherein the anode of the first diode is connected, along with the anode of the second diode and via a third resistor, to the supply potential, wherein the emitters of the fifth transistor and of the sixth transistor are coupled to reference potential via a source of constant current, wherein the base of the sixth transistor comprises one of the multiplier's input terminals and the base of the fifth transistor comprises the other input terminal, wherein the first four transistors are multiple-emitter transistors, wherein each emitter of the first transistor is connected to one emitter of the second transistor and to the current-input terminal of a source of variable current, wherein the current-output terminal of the respective source of variable current is connected to reference potential, wherein the control-input terminal of each of said respective sources of variable current are non-inverting input terminals, such that each emitter of the third transistor is connected to a corresponding emitter of the fourth transistor and to the current-input terminal of an individual source of variable current, such that each current-output terminal of each of said respective sources of variable current is connected to reference potential, and wherein the control-input terminals of said sources of variable current are inverting input terminals.
Claim 3
Dependent Claim
169 words
A four-quadrant multiplier in accordance with claim 1, wherein the first four transistors are substantially identical multiple-emitter transistors, such that each emitter of the first transistor is connected to a corresponding emitter of the second transistor and to the collector of a seventh transistor, wherein each emitter of the third transistor is connected to one emitter of the fourth transistor and to the collector of an eighth transistor, wherein the emitter of each of said transistors having its collector connected to an emitter of the first transistor is connected via a coupling resistor to one emitter of a transistor with its collector connected to the emitter of the third transistor, wherein the terminals of each coupling resistor are connected, via a separate source of constant current, to reference potential, such that the base of the seventh transistor and the bases of the other like connected transistors are non-inverting input terminals, and wherein the base of the eighth transistor and the bases of the other transistors are inverting input terminals.
Claim 4
Dependent Claim
55 words
A monolithic integrated four-quadrant multiplier in accordance with claim 1, wherein the sources of variable current connected to the inverting and non-inverting input terminals are in the form of sources of constant current which can be coupled and decoupled, and wherein square-wave signals are applied to the signal inputs formed by the corresponding input terminals.
Claim 5
Dependent Claim
101 words
A monolithic integrated four-quadrant multiplier in accordance with claim 1, wherein each of the non-inverting input terminals other than the first non-inverting input terminal is connected to one output terminal of a particular I 2 L gate, wherein each of the inverting input terminals other than the second inverting input terminal is connected to the other output terminal of said particular I 2 L gate, such that the inverse signal is added to the signal appearing at the first output terminal, whereby each input terminal of a particular gate is provided with a square-wave signal that is related to reference potential.
Claim 6
Dependent Claim
51 words
A four quadrant multiplier in accordance with claim 1, wherein the emitters of the fifth transistor and of the sixth transistor are interconnected via a fourth resistor and a fifth resistor, wherein the junction between the fourth and fifth resistors is coupled to reference potential via said source of constant current.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |