EP0157520A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Analog multiplier with improved linearity
Assignee: Precision Monolithics Inc
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Filing: 1985-03-14
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Granted: —
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Expires: 2005-03-14
Abstract
Abstract An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors (Q7, Q8;Q9,Q10) provide base drive currents to the amplifiertran- sistors (Q3, Q4; Q5, Q6), one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors (Q3, Q4; Q5, Q6) has a common base connection with a matching transistor (Q15, Q16; Q17, Q18) that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors (Q3, Q15; Q4, Q16; Q5, Q17; Q6, Q18) substantially independent of the Y voltage signal. Separate current sources (16,17) also supply the standing base currents for the transistors (Q3, Q4) on one of the amplifiers, thereby correcting for static imbalances in the base drive circuitry.
Inventors
- 👤 Derek F. Bowers
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 03:10
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
378 words
In an analog multiplier circuit for multiplying two signals X and Y, the circuit including current sources (I1,I2,I3,I4) having magnitudes xI B , (1-x)I B , yI E and (1-y)I E , where x and y are dimensionless indices of X and Y, respectively, in the range zero to unity and I B and I E are fixed currents, first and second differential amplifiers each comprising a pair of bipolar transistors (Q3,Q4; Q5,Q6) with a common collector-emitter circuit connection; the yI E and (1-y)I E current sources (13,14) connected to supply current to the first and second amplifiers, respectively, said amplifiers providing an output (2,4) for the multiplier circuit, and a base drive circuit (Q1,Q2) connected in circuit with the xI B and (1-x)I B current sources (11,12) to provide base drive current to said amplifier transistors, the improvement comprising a base drive circuit which comprises: first (Q7) and second (Q8) bipolar transistors having their collector-emitter circuits connected in circuit with the xI B and (1-x)IB sources (11,12), respectively, third (Q9) and fourth (Q10) bipolar transistors having their collector-emitter circuits connected in circuit with the xI B and (1-x)IB current sources (I1,I2), respectively, means connecting the collector-emitter circuits of the first and second transistors (Q7,Q8) to provide base drive currents to respective transistors (Q4,Q3) in the first amplifier, means connecting the collector-emitter circuits of the third and fourth transistors (Q9,Q10) to provide base drive currents to respective transistors (Q6,Q5) in the second amplifier, first bias means (BIAS 1) connected to apply bias voltages to the bases of the first and second transistors (Q7,Q8), first voltage trimming means (Tl) connected to apply a trimming voltage differential between the bases of the first and second transistors (Q7,Q8) and thereby adjust the voltage offset between those transistors, second bias means (BIAS 2) connected to apply bias voltages to the bases of the third and fourth transistors (Q9,Q10), and second voltage trimming means (T2) connected to apply a trimming voltage differential between the bases of the third and fourth transistors (T9,T10) independently of the first voltage trimming means (Tl), and thereby independently adjust the voltage offset between those transistors, whereby nonlinearities between the multiplier circuit output and the X voltage signal may be reduced by appropriate trimming of said base voltage differentials.
Claim 2
Dependent Claim
378 words
In an analog multiplier circuit for multiplying two signals X and Y, the circuit including current sources (I1,I2,I3,I4) having magnitudes xI B , (1-x)I B , yI E and (1-y)I E , where x and y are dimensionless indices of X and Y, respectively, in the range zero to unity and I B and I E are fixed currents, first and second differential amplifiers each comprising a pair of bipolar transistors (Q3,Q4; Q5,Q6) with a common collector-emitter circuit connection; the yI E and (1-y)I E current sources (13,14) connected to supply current to the first and second amplifiers, respectively, said amplifiers providing an output (2,4) for the multiplier circuit, and a base drive circuit (Q1,Q2) connected in circuit with the xI B and (1-x)I B current sources (11,12) to provide base drive current to said amplifier transistors, the improvement comprising a base drive circuit which comprises: first (Q7) and second (Q8) bipolar transistors having their collector-emitter circuits connected in circuit with the xI B and (1-x)IB sources (11,12), respectively, third (Q9) and fourth (Q10) bipolar transistors having their collector-emitter circuits connected in circuit with the xI B and (1-x)IB current sources (I1,I2), respectively, means connecting the collector-emitter circuits of the first and second transistors (Q7,Q8) to provide base drive currents to respective transistors (Q4,Q3) in the first amplifier, means connecting the collector-emitter circuits of the third and fourth transistors (Q9,Q10) to provide base drive currents to respective transistors (Q6,Q5) in the second amplifier, first bias means (BIAS 1) connected to apply bias voltages to the bases of the first and second transistors (Q7,Q8), first voltage trimming means (Tl) connected to apply a trimming voltage differential between the bases of the first and second transistors (Q7,Q8) and thereby adjust the voltage offset between those transistors, second bias means (BIAS 2) connected to apply bias voltages to the bases of the third and fourth transistors (Q9,Q10), and second voltage trimming means (T2) connected to apply a trimming voltage differential between the bases of the third and fourth transistors (T9,T10) independently of the first voltage trimming means (Tl), and thereby independently adjust the voltage offset between those transistors, whereby nonlinearities between the multiplier circuit output and the X voltage signal may be reduced by appropriate trimming of said base voltage differentials.
Claim 3
Dependent Claim
37 words
The analog multiplier circuit of claim 1, wherein the collector-emitter circuits of the first and third transistors (Q7,Q9) are connected in series, and the collector-emitter circuits of the second and fourth transistors (Q8,Q10) are connected in series.
Claim 4
Dependent Claim
62 words
The analog multiplier circuit of claim 1, the first and second transistors (Q7,Q8) being connected so that their collector-emitter currents supply both the collector-emitter currents of the third and fourth transistors (Q9,Q10) and the base currents of the first amplifier transistors (Q4,Q3), respectively, and further comprising current source means (16,17) connected to supply the standing base currents of the first amplifier transistors.
Claim 5
Dependent Claim
18 words
The analog multiplier circuit of claim 1, wherein said first and second transistors (Q7,Q8) are connected as diodes.
Claim 6
Dependent Claim
35 words
The analog multiplier circuit of claim 1, wherein said first and second voltage trimming means (Tl,T2) are adapted to apply trimming voltages which are substantially directly proportional to absolute temperature over a predetermined temperature range.
Claim 7
Dependent Claim
193 words
The analog multiplier circuit of claim 1, 2, 3, 4 or 5, further comprising circuitry to make collector-emitter current imbalances between the first and second transistors (Q7,Q8) on the one hand and the third and fourth transistors (Q9,Q10) on the other hand independent of the Y voltage signal and thereby reduce nonlinearities between the multiplier circuit output and the Y voltage signal, said circuitry comprising: fifth and sixth bipolar transistors (Q15,Q16) matched with and having a common base connection with respective ones of the transistors (Q3,Q4) in the first differential amplifier, the collector-emitter circuits of said fifth and sixth transistors (Q15,Q16) connected to be supplied with current by the (1-y)IE current source (14), and seventh and eighth bipolar transistors (Q17,Q18) matched with and having a common base connection with respective ones of the transistors (Q5,Q6) in the second differential amplifier, the collector-emitter circuits of said seventh and eighth transistors (Q17,Q18) connected to be supplied by the yI E current source (13), whereby the base drive currents provided by the first through fourth transistors (Q7,Q8,Q9,Q10) are substantially proportional to yI E + (1-y)I E , and thereby substantially independent of the Y voltage signal.
Claim 8
Dependent Claim
304 words
In an analog multiplier circuit for multiplying two signals X and Y, the circuit including current sources (Il,I2,I3,I4) having magnitudes xI B , (1-x)I B , yI E and (1-y)I E , where x and y are dimensionless indices of X and Y, respectively, in the range zero to unity and I B and I E are fixed currents, first and second differential amplifiers each comprising a pair of bipolar transistors (Q3,Q4; Q5,Q6) with a common collector-emitter circuit connection, the yI E and (1-y)I E current sources (13,14) connected to supply current to the first and second amplifiers, respectively, said amplifiers providing an output (2,4) for the multiplier circuit, and a base drive circuit (Ql,Q2) connected in circuit with the xI B and (1-x)IB current sources (11,12) to provide base drive currents to said amplifier transistors, the improvement comprising circuitry to make imbalances between said base drive currents substantially independent of the Y voltage signal, and thereby reduce nonlinearities between the multiplier circuit output and the Y voltage signal, said circuitry comprising: a plurality of compensation bipolar transistors (Q15,Q16,Q17,Q18) matched with and having common base connections with respective ones of the amplifier transistors (Q3,Q4,Q5,Q6), the compensation transistors (Q15,Q16) which have a common base connection with the amplifier transistors (Q3,Q4) supplied by the yI E current source (13) having their collector-emitter circuits connected to be supplied with current from the (1-y)I E current source (14), and the compensation transistors (Q17,Q18) which have a common base connection with the amplifier transistors (Q5,Q6) supplied by the (1-y)I E current source (14) having their collector-emitter circuits connected to be supplied with current from the yI E current source (13), whereby the base drive currents provided by said base drive circuit are substantially proportional to y I E + (1-y)IE, and thereby substantially independent of the Y voltage signal.
Claim 9
Dependent Claim
304 words
In an analog multiplier circuit for multiplying two signals X and Y, the circuit including current sources (Il,I2,I3,I4) having magnitudes xI B , (1-x)I B , yI E and (1-y)I E , where x and y are dimensionless indices of X and Y, respectively, in the range zero to unity and I B and I E are fixed currents, first and second differential amplifiers each comprising a pair of bipolar transistors (Q3,Q4; Q5,Q6) with a common collector-emitter circuit connection, the yI E and (1-y)I E current sources (13,14) connected to supply current to the first and second amplifiers, respectively, said amplifiers providing an output (2,4) for the multiplier circuit, and a base drive circuit (Ql,Q2) connected in circuit with the xI B and (1-x)IB current sources (11,12) to provide base drive currents to said amplifier transistors, the improvement comprising circuitry to make imbalances between said base drive currents substantially independent of the Y voltage signal, and thereby reduce nonlinearities between the multiplier circuit output and the Y voltage signal, said circuitry comprising: a plurality of compensation bipolar transistors (Q15,Q16,Q17,Q18) matched with and having common base connections with respective ones of the amplifier transistors (Q3,Q4,Q5,Q6), the compensation transistors (Q15,Q16) which have a common base connection with the amplifier transistors (Q3,Q4) supplied by the yI E current source (13) having their collector-emitter circuits connected to be supplied with current from the (1-y)I E current source (14), and the compensation transistors (Q17,Q18) which have a common base connection with the amplifier transistors (Q5,Q6) supplied by the (1-y)I E current source (14) having their collector-emitter circuits connected to be supplied with current from the yI E current source (13), whereby the base drive currents provided by said base drive circuit are substantially proportional to y I E + (1-y)IE, and thereby substantially independent of the Y voltage signal.
References Cited (Backward Citations)
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