Controllable multiplier circuit with expanded gain control range

Claim 2

A multiplying circuit comprising first and second transistors arranged in a long-tailed pair configuration having a collector output and interconnected emitter electrodes coupled to a first current source, a bias voltage adjusting circuit for applying equal base bias voltages to the base electrodes of the first and second transistors, means connecting said base electrodes to a signal input, a controlled current distribution circuit including a shunting transistor having a collector-emitter path DC coupled in parallel with said first and second transistors, and a control circuit for applying a control voltage between a base electrode of the shunting transistor and the base electrodes of the first and second transistors.

Claim 3

A multiplying circuit as claimed in claim 1, wherein the first current source is controllable and coupled to the control circuit, and the control circuit includes a threshold circuit for a sequential control of the first current source and the current distribution circuit.

Claim 4

A multiplying circuit as claimed in claim 2, characterized in that the current distibution circuit is connected to a control input of the control circuit via the threshold circuit, said threshold circuit including a series arrangement of two resistors for producing thereacross a control voltage for the first controllable current source and the current distribution circuit, and means coupling an output of the threshold circuit via a first control resistor to a reference voltage for producing thereacross a variable part of said control voltage between the base of the shunting transistor and the bases of the first and second transistors.

Claim 5

A multiplying circuit as claimed in claims 1 or 2 wherein the control circuit includes a second controllable current source connected to a control input of the current distribution circuit.

Claim 6

A multiplying circuit as claimed in claim 3 wherein the control circuit includes a second controllable current source connected to a control input of the current distribution circuit, means coupling to the reference voltage the base of the first transistor via the first control resistor, the base of the second transistor via a second control resistor and the base of the shunting transistor via a biasing resistor, said second controllable current source having first and second current outputs coupled to the bases of the first and second transistors, respectively, for varying the base-emitter voltages of the first and second transistors to the same extent in the case of a control of the second controllable current source.

Claim 7

A multiplying circuit as claimed in claims 1 or 2 wherein the first controllable current source is coupled to an aerial signal input and comprises first and second balanced outputs, the first output being coupled to the emitter electrodes of said first and second transistors and the second output being coupled to emitter electrodes of third and fourth transistors, a second shunting transistor of the controlled current distribution circuit being DC connected in parallel with the collector emitter paths of the third and fourth transistors, the base electrodes of the first and fourth transistors being AC connected to ground and the base electrodes of the second and third transistors being connected to a signal terminal of the signal input, and a controllable oscillator connected to the signal terminal.

Claim 8

A multiplying circuit as claimed in claims 1 or 2 wherein the emitter surface area of the first and of the second transistor is larger than that of the shunting transistor.

Claim 9

A multiplying circuit as claimed in claim 6, wherein the collectors of the first and third transistors are connected to the supply line and the collectors of a second and fourth transistors to a signal output, said signal output being coupled to the supply line via a series arrangement of a resistor and two limiting diodes connected in antiparallel.

Claim 10

A multiplying circuit comprising a pair of first and second transistors arranged in a long-tailed pair configuration and having a collector connected to an output terminal and interconnected emitter electrodes coupled to a first controllable current source, a bias voltage adjusting circuit for applying equal base bias voltages to respective base electrodes of the first and second transistors, means coupling said base electrodes to a first signal input means, second signal input means coupled to a control terminal of the first controllable current source, a controlled current distribution circuit including a third transistor DC coupled in shunt with said first and second transistors, and a control circuit for applying a control voltage to the base electrodes of said first, second and third transistors such that an increase of signal current from the first current source causes an increase in the control voltage at the base of the third transistor relative to that at the bases of the first and second transistors.

Claim 11

A multiplying circuit comprising a pair of first and second transistors arranged in a long-tailed pair configuration and having a collector connected to an output terminal and interconnected emitter electrodes coupled to a first controllable current source, a bias voltage adjusting circuit for applying equal base bias voltages to respective base electrodes of the first and second transistors, means coupling said base electrodes to a first signal input means, second signal input means coupled to a control terminal of the first controllable current source, a controlled current distribution circuit including a third transistor DC coupled in shunt with said first and second transistors, and a control circuit for applying a control voltage to the base electrodes of said first, second and third transistors such that an increase of signal current from the first current source causes an increase in the control voltage at the base of the third transistor relative to that at the bases of the first and second transistors.

Claim 12

A multiplying circuit as claimed in claim 9 further comprising a control terminal for applying a control voltage to an input of said control circuit and to an input of said first current source.

Claim 13

A multiyling circuit as claimed in claim 10 wherein said control circuit includes means for controlling the operation of the current distribution circuit and a threshold circuit that inhibits operation thereof for signals below a given level thereby to produce a sequential control of said first and second transistors by said first current source and said current distribution circuit.

Claim 14

A multiplying circuit as claimed in claim 9 further comprising a pair of fourth and fifth transistors arranged in a long-tailed pair configuration and having a collector connected to said output terminal and interconnected emitter electrodes coupled to said first controllable current source, means connecting the base electrodes of the fourth and fifth transistors to the base electrodes of the second and first transistors, respectively, said current distribution circuit including a sixth transistor DC coupled in shunt with said fourth and fifth transistors, and wherein said control circuit applies a control voltage to the base electrodes of said fourth, fifth and sixth transistors.