US4963767A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-level ECL multiplexer without emitter dotting
Assignee: Fairchild Semiconductor Corp
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Filing: 1988-08-25
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Granted: 1990-10-16
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Expires: 2008-08-25
Abstract
Abstract A two-level 4:1 ECL multiplexer circuit comprising two 2:1 multiplexer circuits "OR'd" together prior to a shared output stage. A differential Select line, operable at the same voltage level as the input data lines to the 2:1 multiplexer circuits selects one of the input lines to each 2:1 multiplexer circuit. A second Select line, operable at a different voltage level, selects one or the other of the 2:1 multiplexer circuits. This arrangement functions to eliminate an undesirable glitch observed when selecting data inputs in known two-level, 4:1 multiplexers which use emitter dotting.
Inventors
- 👤 Nguyen X. Sinh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:10
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
A 4:1 multiplexer circuit comprising: first and second 2:1 ECL multiplexer circuits receiving first and second pairs of input lines, respectively, at a first voltage level, wherein said 2:1 multiplexer circuits share a common output stage and have respective outputs connected together prior to said output stage; a differential Select line operable at said first voltage level and having first and second complementary sides, wherein said first side is connected in logic "OR" arrangement with a first input line of each said pair and said second side is connected in logic "OR" arrangement with the second input line of each said pair, whereby said differential Select line operates to select one of said input lines for each of said 2:1 multiplexer circuits; and a second Select line operable at a second voltage level and operatively associated with said first and second 2:1 multiplexer circuits to select one of said circuits, whereby a signal on one of said selected input lines is provided to said common output stage.
Claim 2
Dependent Claim
167 words
A 4:1 multiplexer circuit comprising: first and second 2:1 ECL multiplexer circuits receiving first and second pairs of input lines, respectively, at a first voltage level, wherein said 2:1 multiplexer circuits share a common output stage and have respective outputs connected together prior to said output stage; a differential Select line operable at said first voltage level and having first and second complementary sides, wherein said first side is connected in logic "OR" arrangement with a first input line of each said pair and said second side is connected in logic "OR" arrangement with the second input line of each said pair, whereby said differential Select line operates to select one of said input lines for each of said 2:1 multiplexer circuits; and a second Select line operable at a second voltage level and operatively associated with said first and second 2:1 multiplexer circuits to select one of said circuits, whereby a signal on one of said selected input lines is provided to said common output stage.
Claim 3
Dependent Claim
24 words
The circuit of claim 1 wherein said second Select line is connected to gate current flow through said first and second 2:1 multiplexer circuits.
Claim 4
Dependent Claim
14 words
The circuit of claim 1 wherein said common output stage comprises a common emitter-follower.
Claim 5
Dependent Claim
120 words
A 4:1 ECL multiplexer circuit comprising: first and second pairs of emitter-coupled differential amplifiers, each said amplifier receiving an input line at a first voltage level; a differential Select line having first and second sides operable at said first voltage level, said sides being coupled to respectively enable and disable the amplifiers of each said pair, whereby an amplifier and associated input line are selected from each said pair; a second Select line operable at a second voltage level and coupled to respectively enable and disable said first and second amplifier pairs, whereby one of said pairs is selected; and an output stage coupled to said amplifiers, wherein said amplifiers have respective outputs connected together prior to said output stage.
Claim 6
Dependent Claim
120 words
A 4:1 ECL multiplexer circuit comprising: first and second pairs of emitter-coupled differential amplifiers, each said amplifier receiving an input line at a first voltage level; a differential Select line having first and second sides operable at said first voltage level, said sides being coupled to respectively enable and disable the amplifiers of each said pair, whereby an amplifier and associated input line are selected from each said pair; a second Select line operable at a second voltage level and coupled to respectively enable and disable said first and second amplifier pairs, whereby one of said pairs is selected; and an output stage coupled to said amplifiers, wherein said amplifiers have respective outputs connected together prior to said output stage.
Claim 7
Dependent Claim
51 words
The multiplexer of claim 4, wherein each said amplifier includes a first transistor gated by the associated input line at said first voltage level and a second transistor connected in parallel with said first transistor and gated at said first voltage level by a respective side of said differential Select line.
Claim 8
Dependent Claim
12 words
The multiplexer of claim 5, wherein said output stage comprises an emitter-follower.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |