US4196358A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog multiplexer
Assignee: National Semiconductor Corp
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Filing: 1977-08-16
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Granted: 1980-04-01
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Expires: 1997-08-16
Abstract
Abstract An analog multiplexer connected to a plurality of input terminals selectively samples the input terminals in response to signals from a controller. The multiplexer includes a sample and ramp amplifier circuit for supplying the selected analog input to desired subsequent circuitry, for example, an analog-to-digital converter. The analog multiplexer is particularly useful in applications wherein a microprocessor periodically senses selected analog sensors and applies signals to control devices to regulate the conditions being sensed.
Inventors
- 👤 John C. Conover
- 👤 Larry J. Kendall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:24
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
144 words
A multiplexing circuit comprising: a first conducting line, a second conducting line, a plurality of input cells, each cell having: an input terminal connected to receive electrical signals, a first transistor connected to the input terminal, to a node and to the second line, a second transistor connected between the node and the first line, and means for supplying electrical current to the node during selected periods, said means including a current supply connected to the node and a switch connected between the node and ground; an output terminal connected to the first line; and wherein the switches of all but one of the plurality of input cells are closed at any given time to thereby allow the electrical signals supplied to the input terminal of the cell having an open switch to be supplied to the output terminal connected to the first line.
Claim 2
Dependent Claim
144 words
A multiplexing circuit comprising: a first conducting line, a second conducting line, a plurality of input cells, each cell having: an input terminal connected to receive electrical signals, a first transistor connected to the input terminal, to a node and to the second line, a second transistor connected between the node and the first line, and means for supplying electrical current to the node during selected periods, said means including a current supply connected to the node and a switch connected between the node and ground; an output terminal connected to the first line; and wherein the switches of all but one of the plurality of input cells are closed at any given time to thereby allow the electrical signals supplied to the input terminal of the cell having an open switch to be supplied to the output terminal connected to the first line.
Claim 3
Dependent Claim
40 words
A multiplexing circuit as in claim 1 including means for causing the potential of the output terminal to be equal to the potential of the electrical signals supplied to any of the plurality of input terminals during the selected periods.
Claim 4
Dependent Claim
13 words
A multiplexing circuit as in claim 1 wherein the switch is a transistor.
Claim 5
Dependent Claim
37 words
A multiplexing circuit as in claim 3 wherein the means for causing the potential of the output terminal to be equal to the potential of the electrical signals supplied to the input terminal comprises a current mirror.
Claim 6
Dependent Claim
33 words
A multiplexing circuit as in claim 4 wherein the current mirror comprises a third transistor connected to the second line and a fourth transistor connected between the third transistor and the first line.
Claim 7
Dependent Claim
20 words
A multiplexing circuit as in claim 5 wherein each of the first, second, third and fourth transistors are bipolar transistors.
Claim 8
Dependent Claim
56 words
A multiplexing circuit as in claim 6 wherein: the collector and the base of the third transistor are connected to the second line and to the base of the fourth transistor; the collector of the fourth transistor is connected to the first line; and the emitters of the third and fourth transistors are connected to ground.
Claim 9
Dependent Claim
71 words
A multiplexing circuit as in claim 1 wherein: the base of the first transistor is connected to the input terminal, the emitter of the first transistor is connected to the node, and the collector of the first transistor is connected to the second line, and the emitter of the second transistor is connected to the node, and the base and collector of the second transistor are connected to the first line.
Claim 10
Dependent Claim
46 words
A multiplexing circuit as in claim 8 wherein the base of an offset transistor is connected to the input terminal, the emitter of the offset transistor is connectd to the base of the first transistor and the collector of the offset transistor is connected to ground.
Claim 11
Dependent Claim
45 words
A multiplexing circuit as in claim 5 wherein: the output terminal is connected to a fifth transistor, a sixth transistor is connected to the fifth transistor, a capacitor is connected to the sixth transistor, and a second output terminal is connected to the sixth transistor.
Claim 12
Dependent Claim
60 words
A multiplexing circuit as in claim 10 wherein: the output terminal is connected to the base of the fifth transistor, the emitter of the sixth transistor is connected to the emitter of the fifth transistor, the capacitor is connected to the collector of the sixth transistor, and the second output terminal is connected to the base of the sixth transistor.
Claim 13
Dependent Claim
54 words
A multiplexing circuit as in claim 11 wherein: the collector of the seventh transistor is connected to the emitters of the fifth and sixth transistors, the emitter of the seventh transistor is connected to a current supply, and the base of the seventh transistor is connected through a ramp switch to a current supply.
Claim 14
Dependent Claim
63 words
A multiplexing circuit as in claim 12 wherein: the collector of the fifth transistor is connected to the collector of an eighth transistor, the collector of the sixth transistor is connected to the collector of a ninth transistor, p1 the bases of the eighth and ninth transistors are connected togehter, and the emitters of the eighth and ninth transistors are connected to ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-01 | 1983-10-01 | 1984-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-01 | 1987-10-01 | 1988-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-01 | 1991-10-01 | 1992-04-01 | $7700.00 | Window Closed / Lapsed |