Switched impedance comparator

Claim 2

A synchronous comparator circuit, comprising: a pair of differential input terminals; a pair of output terminals for providing an amplified output signal indicative of the polarity of the differential input signal; amplifier means coupled to the input terminals and the output terminals; and switch means coupled to the amplifier means and switchable under control of a clocking signal between a first state in which the amplifier means has a positive feedback loop gain of less than unity and the differential signal on the input terminals is coupled to a pair of internal switched impedance nodes, and a second state in which the input terminals are isolated from the switched impedance nodes, and the amplifier means has a positive feedback loop gain of greater than unity, to provide an amplified output signal at the output terminals.

Claim 3

A comparator circuit as defined in claim 1, wherein: the switch means in its first state is operative to connect a low impedance across the internal switched impedance nodes, thereby reducing the positive feedback loop gain to below unity and minimizing the effect of positive feedback; and the switch means in its second state is operative to connect a high impedance across the internal switched impedance nodes, thereby permitting a positive feedback loop gain of greater than unity and providing a greatly amplified output signal.

Claim 4

A comparator circuit as defined in claim 2, wherein the amplifier means includes: an acquisition amplifier having a pair of semiconductor amplifier devices; and a latch amplifier having a pair of cross-connected semiconductor amplifier devices, in which the output of each device is coupled to the input of the other, to form a positive feedback loop.

Claim 5

A comparator circuit as defined in claim 3, wherein the switch means includes: first switch means for selectively connecting a relatively low impedance between the internal switched impedance nodes; and second switch means for isolating the acquisition amplifier from the internal switched impedance nodes.

Claim 6

A comparator circuit as defined in claim 4, wherein: the amplifiers and switch means are implemented as semiconductor field-effect transistors.

Claim 7

A comparator circuit as defined in claim 4, wherein: the amplifiers and switch means are implemented as semiconductor bipolar transistors.

Claim 8

A comparator circuit for use in an analog-to-digital converter, the comparator circuit comprising: a pair of differential input terminals for receiving a differential input signal; a pair of output terminals for providing an amplified output signals indicative of the polarity of the differential input signal; an acquisition amplifier coupled to the input terminals, for acquiring and amplifying the differential input signal; a latch amplifier for latching the acquired signal into a pair of internal switched impedance nodes, and for providing amplification between the internal nodes and the output terminals; and switch means switchable by clocking signals between a first state and a second state, the first state being one in which the acquisition amplifier and the latch amplifier are coupled together to acquire the input signal into the internal switched impedance nodes, and in which the latch amplifier provides a positive feedback loop gain of less than unity, and the second state being one in which the acquisition amplifier is isolated from the latch amplifier, and the latch amplifier provides a positive feedback loop gain of greater than unity, to yield an amplified output signal, at the output terminals, indicative of the polarity of the differential input signal.

Claim 9

A comparator circuit for use in an analog-to-digital converter, the comparator circuit comprising: a pair of differential input terminals for receiving a differential input signal; a pair of output terminals for providing an amplified output signals indicative of the polarity of the differential input signal; an acquisition amplifier coupled to the input terminals, for acquiring and amplifying the differential input signal; a latch amplifier for latching the acquired signal into a pair of internal switched impedance nodes, and for providing amplification between the internal nodes and the output terminals; and switch means switchable by clocking signals between a first state and a second state, the first state being one in which the acquisition amplifier and the latch amplifier are coupled together to acquire the input signal into the internal switched impedance nodes, and in which the latch amplifier provides a positive feedback loop gain of less than unity, and the second state being one in which the acquisition amplifier is isolated from the latch amplifier, and the latch amplifier provides a positive feedback loop gain of greater than unity, to yield an amplified output signal, at the output terminals, indicative of the polarity of the differential input signal.

Claim 10

A comparator circuit as defined in claim 7, wherein: the switch means in its first state is operative to connect a low impedance across the internal switched impedance nodes, thereby reducing the feedback loop gain to below unity and minimizing the effect of positive feedback; and the switch means in its second state is operative to connect a high impedance across the internal switched impedance nodes, thereby permitting a positive feedback loop gain of greater than unity and providing an amplified output signal.

Claim 11

A comparator circuit as defined in claim 8, wherein: the acquisition amplifier includes a pair of semiconductor amplifier devices; and the latch amplifier includes a pair of cross-coupled semiconductor amplifier devices, in which the output of each device is coupled to the input of the other, to form a positive feedback loop.

Claim 12

A comparator circuit as defined in claim 9, wherein the switch means includes: first switch means for selectively connecting a relatively low impedance between the internal switched impedance nodes; and second switch means for isolating the acquisition amplifier from the internal switched impedance nodes.

Claim 13

A comparator circuit as defined in claim 10, wherein: the amplifiers and switch means are implemented as semiconductor field-effect transistors.

Claim 14

A comparator circuit as defined in claim 10, wherein: the amplifiers and switch means are implemented as semiconductor bipolar transistors.

Claim 15

A synchronous comparator circuit, comprising: a comparator switchable to an acquisition mode, for rapidly acquiring an analog differential input signal and latching it into a pair of switched impedance nodes, and switchable to a regeneration mode in which the latched signal is amplified to provide an output signal indicative of the polarity of the differential input signal; and switch means for alternately selecting the acquisition mode, which provides a latch amplifier positive feedback loop gain of less than unity, and the regeneration mode, which provides a latch amplifier positive feedback loop gain of greater than unity.

Claim 16

A synchronous comparator circuit, comprising: a comparator switchable to an acquisition mode, for rapidly acquiring an analog differential input signal and latching it into a pair of switched impedance nodes, and switchable to a regeneration mode in which the latched signal is amplified to provide an output signal indicative of the polarity of the differential input signal; and switch means for alternately selecting the acquisition mode, which provides a latch amplifier positive feedback loop gain of less than unity, and the regeneration mode, which provides a latch amplifier positive feedback loop gain of greater than unity.

Claim 17

A comparator circuit as defined in claim 13, wherein the switch means includes: first switch means for selecting a low impedance between the switched impedance nodes in the acquisition mode, to reduce the feedback loop gain, and a high impedance between the nodes in the regeneration mode; and second switch means for isolating the differential input signal from the switched impedance nodes in the acquisition mode.

Claim 18

A comparator circuit as defined in claim 14, wherein: the first switch means operates before the second switch means during transition between the acquisition mode and the regeneration mode, to preserve the acquired signal until regeneration begins.

Claim 21

A method as defined in claim 16, and further including the steps of: switching the comparator configuration alternately between the acquisition phase and the regeneration phase, to provide amplified outputs indicative of the polarities of successively acquired differential input signals.

Claim 22

A method as defined in claim 16, wherein the step of switching the comparator configuration includes: first switching the impedance of the switched nodes from a low to a high value to provide a positive feedback loop gain greater than unity; and then isolating the input terminals from the switched impedance nodes.

Claim 23

A synchronous comparator circuit operable with a clocking signal, having: amplifier means including two input terminals, output terminals and switched impedance nodes coupled to the input terminals and the output terminals, and having a positive feedback loop gain; and switch means coupled to the amplifier means, and switchable under control of the clocking signal between a first state in which the impedance of the amplifier switched impedance nodes is at a low level and said circuit has a positive feedback loop gain of less than unity, and a second state in which the impedance of the switched impedance nodes is at a high level relative to said first state and the circuit has a positive feedback loop gain of greater than unity to provide an amplified output signal at the output terminals.

Claim 24

A synchronous comparator circuit operable with a clocking signal, having: amplifier means including two input terminals, output terminals and switched impedance nodes coupled to the input terminals and the output terminals, and having a positive feedback loop gain; and switch means coupled to the amplifier means, and switchable under control of the clocking signal between a first state in which the impedance of the amplifier switched impedance nodes is at a low level and said circuit has a positive feedback loop gain of less than unity, and a second state in which the impedance of the switched impedance nodes is at a high level relative to said first state and the circuit has a positive feedback loop gain of greater than unity to provide an amplified output signal at the output terminals.

Claim 25

A comparator circuit as defined in claim 19, wherein: the switch means in its first state is operative to connect a low impedance across the switched impedance nodes, thereby reducing the positive feedback loop gain to below unity and minimizing the effect of positive feedback; and the switch means in its second state is operative to connect a high impedance across the switched impedance nodes, thereby permitting a positive feedback loop gain of greater than unity and providing a greatly amplified output signal.

Claim 26

A comparator circuit as defined in claim 20, wherein the amplifier means includes: an acquisition amplifier having a pair of semiconductor amplifier devices; and a latch amplifier having a pair of cross-connected semiconductor amplifier devices, in which the output of each device is coupled to the input of the other, to form the positive feedback loop.

Claim 27

A comparator circuit as defined in claim 21, wherein the switch means includes: first switch means for selectively connecting a relatively low impedance between the switched impedance nodes during an acquisition mode of operation; and second switch means for isolating the acquisition amplifier from the switched impedance nodes during the acquisition mode of operation.

Claim 28

A comparator circuit as defined in claim 22, wherein: the amplifiers and switch means are implemented as semiconductor field-effect transistors.

Claim 29

A comparator circuit as defined in claim 22, wherein: the amplifiers and switch means are implemented as semiconductor bipolar transistors.