US5170079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Collector dot and circuit with latched comparator
Assignee: Sony Corp
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Filing: 1991-10-23
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Granted: 1992-12-08
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Expires: 2011-10-23
Abstract
Abstract A logic circuit which can operate to form a logic AND signal of a predetermined voltage level in accordance with a potential difference between a plurality of input signals using a collector dot AND circuit and a latched comparator circuit without the necessity of provision of a NOT circuit or a level shifting circuit at a preceding stage to the logic circuit. The logic circuit comprises a collector dot AND circuit, a logic level outputting circuit and a plurality of emitter follower circuits. Output electrodes of those of the emitter followers which are connected to receive NOT signals of input signals developed from the collector dot AND circuit are coupled commonly to form a wired OR circuit, and an output of the wired OR circuit is supplied to a transistor of the logic level outputting circuit connected to receive a logic AND signal of the input signals developed from the collector dot AND circuit so as to form a NOT signal of the logic AND signal.
Inventors
- 👤 Yoshihiro Komatsu
- 👤 Yuji Gendai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/20; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
277 words
A logic circuit having a plurality of input terminals, comprising: a collector dot AND circuit connected to said input terminals and capable of developing a logic AND signal and NOT signals of input signals received by way of said input terminals; a logic level outputting circuit composed of a plurality of transistors with the emitters coupled commonly, said transistors being connected to individually receive, at the collectors thereof, signal voltages developed from said collector dot AND circuit; and a plurality of emitter follower circuits each including a transistor connected to receive, at the base thereof, a corresponding one of the signal voltages developed from said collector dot AND circuit; output electrodes of those of said emitter followers which are connected to receive, at the bases thereof, the NOT signals of the input signals developed from said collector dot AND circuit being coupled commonly to form a wired OR circuit which is connected to supply an output thereof to the base of one of said transistors of said logic level outputting circuit which is connected to receive, at the collector thereof, the logic AND signal of the input signals developed from said collector dot AND circuit; an output voltage of one of said emitter followers which is connected to receive, at the base thereof, the logic AND signal of the input signals developed from said collector dot AND circuit being provided to an output terminal of said logic circuit and also to the bases of those of said transistors of said logic level outputting circuit which are connected to receive, at the collectors thereof, the NOT signals of the input signals developed from said collector dot AND circuit.
Claim 2
Dependent Claim
277 words
A logic circuit having a plurality of input terminals, comprising: a collector dot AND circuit connected to said input terminals and capable of developing a logic AND signal and NOT signals of input signals received by way of said input terminals; a logic level outputting circuit composed of a plurality of transistors with the emitters coupled commonly, said transistors being connected to individually receive, at the collectors thereof, signal voltages developed from said collector dot AND circuit; and a plurality of emitter follower circuits each including a transistor connected to receive, at the base thereof, a corresponding one of the signal voltages developed from said collector dot AND circuit; output electrodes of those of said emitter followers which are connected to receive, at the bases thereof, the NOT signals of the input signals developed from said collector dot AND circuit being coupled commonly to form a wired OR circuit which is connected to supply an output thereof to the base of one of said transistors of said logic level outputting circuit which is connected to receive, at the collector thereof, the logic AND signal of the input signals developed from said collector dot AND circuit; an output voltage of one of said emitter followers which is connected to receive, at the base thereof, the logic AND signal of the input signals developed from said collector dot AND circuit being provided to an output terminal of said logic circuit and also to the bases of those of said transistors of said logic level outputting circuit which are connected to receive, at the collectors thereof, the NOT signals of the input signals developed from said collector dot AND circuit.
Claim 3
Dependent Claim
59 words
A logic circuit according to claim 1, wherein said logic level outputting circuit includes an additional transistor connected such that the base is connected to receive the output of said wired OR circuit; the emitter is connected to the emitters of the other transistors of said logic level outputting circuit; and the collector is connected to a power source.
Claim 4
Dependent Claim
111 words
A logic circuit according to claim 1, wherein said logic circuit further has a reference signal input terminal, and said collector dot AND circuit includes a first set of transistors connected to individually receive the input signals at the bases thereof and output NOT signals of the input signals from the collectors thereof, and a second set of transistors individually connected at the emitters thereof to the emitters of corresponding ones of said transistors of said first set and connected to receive, at the bases thereof, a reference signal by way of said reference signal input terminal and output a logic AND signal of the input signals from the collectors thereof.
Claim 5
Dependent Claim
52 words
A logic circuit according to claim 3, wherein said collector dot AND circuit further includes a resistor connected between the collector of each of said transistors of said first set and a power source, and another resistor connected between the collectors of said transistors of said second set and said power source.
Claim 6
Dependent Claim
82 words
A logic circuit according to claim 3, wherein said logic circuit further has a clock signal input terminal, and said collector dot AND circuit further includes a third set of transistors connected such that the bases are connected to said clock signal input terminal to receive a clock signal; the emitters are connected commonly to be supplied with an electric current; and the collectors are individually connected to the emitters of corresponding ones of said transistors of said first and second sets.
Claim 7
Dependent Claim
86 words
A logic circuit according to claim 3, wherein said logic circuit further has a clock signal input terminal, and said collector dot AND circuit further includes a third set of transistors connected such that the bases are connected to said clock signal input terminal to receive a NOT signal of a clock signal; the emitters are connected commonly to be supplied with an electric current; and the collectors are individually connected to the emitters of corresponding ones of said transistors of said first and second sets.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |