US4686674A
Expired / Lapsed
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Multiplexer with inhibit for ECL gate array
Assignee: National Semiconductor Corp
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Filing: 1985-12-12
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Granted: 1987-08-11
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Expires: 2005-12-12
Abstract
Abstract A multiplexer with inhibit is implemented so that an active inhibit signal effectively sets the select signals to block all but the selected input signal and effectively masks the selected input signal. In the case of the disclosed emitter-coupled logic 4:1 multiplexer, enable signal controlled transistors (Q24 and Q25) are in parallel with transistors (Q14 and Q15) respectively controlled by the select signals (S0 and S1). Activating the enable signal (EN) effectively selects one input (A3) and blocks the others (A0, A1 and A2). A third enable activated transistor (Q35) is in parallel with the transistor (Q13) controlled by the selected input (A3). The activated enable masks the selected signal to complete the inhibit function. Thus, a standard function is implemented with a reduced free-standing and total transistor count.
Inventors
- 👤 Nim C. Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:33
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03K17/62; H03K17/6257; H03K17/6264
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
153 words
A multiplexer comprising: means for receiving plural input signals; means for receiving a select signal set including at least one select signal; means for producing an output signal as a function of one of said input signals, said one of said input signals being selected according to the value of said select signal set; means for receiving an inhibit signal; means for logically combining said inhibit signal with said select signal set so that a predetermined exactly one of said input signals is selected when said inhibit signal is active; and means for logically combining said inhibit signal with said predetermined exactly one of said input signals to yield an intermediate signal with a predetermined value when said inhibit signal is active, said two combining means being coupled with said means for producing an output signal so that said output is forced to a predetermined logic level when said inhibit signal is active.
Claim 2
Dependent Claim
153 words
A multiplexer comprising: means for receiving plural input signals; means for receiving a select signal set including at least one select signal; means for producing an output signal as a function of one of said input signals, said one of said input signals being selected according to the value of said select signal set; means for receiving an inhibit signal; means for logically combining said inhibit signal with said select signal set so that a predetermined exactly one of said input signals is selected when said inhibit signal is active; and means for logically combining said inhibit signal with said predetermined exactly one of said input signals to yield an intermediate signal with a predetermined value when said inhibit signal is active, said two combining means being coupled with said means for producing an output signal so that said output is forced to a predetermined logic level when said inhibit signal is active.
Claim 3
Dependent Claim
132 words
A multiplexer comprising: inputs for four data signals, two select signals and an inhibit signal; means for providing an output signal as a function of one of said input signals, as selected according to the values of said select signals; means for logically combining said inhibit signal with said select signal so that a predetermined exactly one of said input signals is selected when the inhibit signal is active; and means for logically combining said inhibit signal with said predetermined exactly one of said input signals to yield an intermediate signal with a predetermined value when said inhibit signal is active, said two combining means being coupled with said means for producing an output signal so that said output is forced to a predetermined logic level when said inhibit signal is active.
Claim 4
Dependent Claim
132 words
A multiplexer comprising: inputs for four data signals, two select signals and an inhibit signal; means for providing an output signal as a function of one of said input signals, as selected according to the values of said select signals; means for logically combining said inhibit signal with said select signal so that a predetermined exactly one of said input signals is selected when the inhibit signal is active; and means for logically combining said inhibit signal with said predetermined exactly one of said input signals to yield an intermediate signal with a predetermined value when said inhibit signal is active, said two combining means being coupled with said means for producing an output signal so that said output is forced to a predetermined logic level when said inhibit signal is active.
Claim 5
Dependent Claim
164 words
An emitter-coupled logic 4:1 multiplexer with inhibit comprising: four input transistors controlled by respective data input signals; first and second select transistors controlled by respective select signals; output means, including means for coupling said input and select transistors, for providing an output signal reflecting one of said input signals as selected by the levels of said select signals; and first, second, and third inhibit transistors controlled by a common inhibit signal, said first inhibit transistor being in parallel with said first select transistor, said second inhibit transistor being in parallel with said second select transistor, and said third inhibit transistor being in parallel with the one of said input transistors selected when said first and second select transistors are set to logic high so that when said inhibit signal is active said output is forced to a predetermined logic level, and when said inhibit is inactive, the output is a function of the data signal selected according to the status of said select signals.
Claim 6
Dependent Claim
164 words
An emitter-coupled logic 4:1 multiplexer with inhibit comprising: four input transistors controlled by respective data input signals; first and second select transistors controlled by respective select signals; output means, including means for coupling said input and select transistors, for providing an output signal reflecting one of said input signals as selected by the levels of said select signals; and first, second, and third inhibit transistors controlled by a common inhibit signal, said first inhibit transistor being in parallel with said first select transistor, said second inhibit transistor being in parallel with said second select transistor, and said third inhibit transistor being in parallel with the one of said input transistors selected when said first and second select transistors are set to logic high so that when said inhibit signal is active said output is forced to a predetermined logic level, and when said inhibit is inactive, the output is a function of the data signal selected according to the status of said select signals.
Claim 7
Dependent Claim
100 words
The multiplexer of claim 1 wherein said means for producing an output signal is coupled to said means for receiving plural input signals and to said means for receiving a select signal set, said means for logically combining said inhibit signal with said select signal set being coupled to said means for receiving said inhibit signal and to said means for receiving a select signal set, said means for logically combining said inhibit signal with said predetermined one of said input signal being coupled to said means for receiving an input signal and said means for receiving plural input signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |