High speed solid state multiplexer

Claim 1

A multiplexing apparatus for receiving a plurality of pairs of input signals, having voltages in a predetermined range, from a plurality of input sources each comprising high and low voltage input sources, and for outputting at least one pair of input signals selected from said plurality of pairs of input signals, comprising: a unit, including: a first plurality of pairs of transistors, the bases of each pair of transistors in said first plurality of pairs of transistors for coupling, respectively, to high and low voltage input sources of one of said input sources; means for applying a predetermined voltage to the collector of each transistor in said first plurality of pairs of transistors; a plurality of pairs of diodes, coupled, respectively, to said first plurality of pairs of transistors such that the anodes of each pair of diodes are coupled, respectively, to the emitters of a corresponding pair of transistors in said first plurality of pairs of transistors; a second plurality of pairs of transistors, coupled, respectively, to said first plurality of pairs of transistors such that the collectors of each pair of transistors in said second plurality of pairs of transistors are coupled, respectively, to the emitters of a corresponding pair of transistors in said first plurality of pairs of transistors, the collector of each transistor in said second plurality of pairs of transistors being coupled to the anode of the same diode in said plurality of pairs of diodes to which a corresponding transistor in said first plurality of pairs of transistors is coupled; means for applying a predetermined voltage to the bases of a selected pair of transistors in said second plurality of pairs of transistors; means for applying a predetermined current to the emitters of said selected pair of transistors in said second plurality of pairs of transistors; a third plurality of pairs of transistors, coupled, respectively, to said first plurality of pairs of transistors such that the emitters of each pair of transistors in said third plurality of pairs of transistors are coupled, respectively, to the emitters of a corresponding pair of transistors in said first plurality of pairs of transistors, the emitter of each transistor in said third plurality of pairs of transistors being coupled to the anode of the same diode, in said plurality of pairs of diodes, to which a corresponding transistor in said first plurality of pairs of transistors is coupled; means for applying a predetermined voltage to the collector of each transistor in said third plurality of pairs of transistors; means for applying a predetermined voltage to the bases of a selected pair of transistors in said third plurality of pairs of transistors; a first output transistor, the base of said first output transistor being coupled to the cathode of a first diode in each pair of said plurality of pairs of diodes; means for applying a predetermined voltage to the collector of said first output transistor; a second output transistor, the base of said second output transistor being coupled to the cathode of a second diode in each pair of said plurality of pairs of diodes; means for applying a predetermined voltage to the collector of said second output transistor; and means, coupled to the cathode of each diode in said plurality of pairs of diodes, for sinking a predetermined portion of said predetermined current applied to the emitters of said selected pair of transistors in said second plurality of pairs of transistors through a pair of diodes, in said plurality of pairs of diodes, coupled to said selected pair of transistors in said second plurality of pairs of transistors.