US3760358A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latching selector for selectively drawing out a single signal from among a plurality thereof
Assignee: Nippon Gakki Co Ltd
•
Filing: 1972-08-08
•
Granted: 1973-09-18
•
Expires: 1992-08-08
Abstract
Abstract A latching selector comprises a plurality of switching circuits each switching an assigned signal, a memory circuit including bistable circuits and controlling the respective switching circuits, and the same plurality of key switches triggering the memory circuit. The switching circuits have respective signal input terminals supplied with respective assigned signals, respective control terminals and a common signal output terminal. The memory circuit includes memory output terminals respectively connected to the control terminals, memory input terminals respectively connected to the key switches, a number of bistable circuits equal to the digit number sufficient for binary notation of the plurality number, and a coding and encoding matrix connecting the memory input and output terminals to the bistable circuits in binary relation. When a key switch is actuated, the bistable circuits memorize in binary notation which key switch has been actuated, and in turn keep the corresponding switching circuit to conduct the assigned signal to signal output terminal until another key switch is next actuated.
Inventors
- 👤 S Isii
- 👤 Y Uchiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:46
CPC Classifications
G; G10; G10H; G10H1/00; G10H1/18; G10H1/22; Y; Y10; Y10S; Y10S84/00; Y10S84/02
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
162 words
A latching selector for selectively drawing out a single signal from a plurality of signals comprising: a. a plurality of switching circuits each having a signal input terminal, a control terminal and a signal output terminal; b. a memory circuit including same said plurality of memory output terminals respectively connected to said control terminals, same said plurality of memory input terminals, bistable circuits in a number equal to the digit number sufficient for binary notation of said plurality number and each having a first and a second lines, and a coding and encoding matrix connecting said memory output terminals and said memory input terminals to either of said first and second lines of said respective bistable circuits in a binary code fashion; c. same said plurality of key switches respectively connected to said respective memory input terminals; and d. and a control voltage source connected to said key switches and having a voltage sufficient for deciding the states of said bistable circuits.
Claim 2
Dependent Claim
162 words
A latching selector for selectively drawing out a single signal from a plurality of signals comprising: a. a plurality of switching circuits each having a signal input terminal, a control terminal and a signal output terminal; b. a memory circuit including same said plurality of memory output terminals respectively connected to said control terminals, same said plurality of memory input terminals, bistable circuits in a number equal to the digit number sufficient for binary notation of said plurality number and each having a first and a second lines, and a coding and encoding matrix connecting said memory output terminals and said memory input terminals to either of said first and second lines of said respective bistable circuits in a binary code fashion; c. same said plurality of key switches respectively connected to said respective memory input terminals; and d. and a control voltage source connected to said key switches and having a voltage sufficient for deciding the states of said bistable circuits.
Claim 3
Dependent Claim
30 words
A latching selector according to claim 1 wherein said means for coupling said output and input terminals of said memory circuit to said lines of said bistable circuits are diodes.
Claim 4
Dependent Claim
96 words
A latching selector according to claim 1 wherein each said key switch includes a normally open fixed contact, a normally closed fixed contact and a movable contact, and wherein said key switches are connected in a preference fashion in such a manner that said movable contact of the respective key switches is connected to the normally closed fixed contact of the adjacent key switch, and the movable contact of the rearmost switch to said control voltage source, said normally open contacts of the respective switches being connected to the corresponding input terminals of said memory circuit.
Claim 5
Dependent Claim
50 words
A latching selector according to claim 1 wherein each said switching circuit includes a transistor having a collector, an emitter and a base, and the respective input terminals of said switching circuit and the respective output terminals of said memory circuit are coupled to the bases of the corresponding transistors.
Claim 6
Dependent Claim
90 words
A latching selector according to claim 1 wherein said memory circuit includes four bistable circuits, thirteen output terminals and thirteen input terminals; and said key switches connected to said input terminals each including a normally open fixed contact, a normally closed fixed contact and a movable contact, said normally open fixed contact being connected to the corresponding input terminal of said memory circuit, said movable contact to the normally closed contact of the adjacent key switch and the movable contact of the rearmost key switch to said control voltage source.
Claim 7
Dependent Claim
59 words
A latching selector according to claim 1 wherein said coding and encoding matrix includes first coupling elements connected in a binary code matrix fashion between said memory output terminals and said lines of the bistable circuits and second coupling elements connected in a binary code matrix fashion between said memory input terminals and said lines of the bistable circuits.
Claim 8
Dependent Claim
162 words
A latching selector according to claim 6 wherein said first and second coupling elements each have a conduction path and a control electrode for controlling the conductivity of said conduction path by the voltage impressed on said control electrode, the conduction path of said first coupling elements being connected between the corresponding memory output terminals and a circuit ground and their control electrodes being connected to the corresponding lines of said bistable circuits, said first coupling elements being rendered conductive when said lines of said bistable circuits to which said control electrodes are connected are set at a first voltage level, the conduction paths of said second coupling elements being connected between said lines of said bistable circuits and a circuit ground and their control electrodes being connected to said memory input terminals, said second coupling elements being rendered conductive when said memory input terminals to which said control electrodes are connected are impressed with the voltage from said control voltage source.
Claim 9
Dependent Claim
46 words
A latching selector according to claim 7 wherein said first and second coupling elements are field effect transistors each having a conduction path formed between a source and a drain and a gate for controlling the conductivity of said conduction path by a voltage impressed thereon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |