US3838296A
Expired / Lapsed
US
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Emitter coupled logic transistor circuit
Assignee: National Semiconductor Corp
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Filing: 1973-10-29
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Granted: 1974-09-24
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Expires: 1993-10-29
Abstract
Abstract In an emitter coupled logic transistor circuit, a plurality of data gates are arranged for multiplexing input data onto a common output means in response to a coded multiplex signal which selects respective data gates sequentially. A common current source is connected to respective ones of said data gates via the intermediary of respective current switch gates, such current switch gates being responsive to the decoded input select command signals for selectively energizing respective ones of said data gates, whereby power consumed by the multiplex circuit is minimized since only a selected data gate is powered up at any given time.
Inventors
- 👤 Leod E Mc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K17/6264; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
127 words
In an emitter coupled logic transistor circuit: a common output means; a plurality of data gate means to which a plurality of respective data input signals are to be applied for gating onto said common output means; current source means common to said plurality of data gates for supplying current thereto; current source gate means connected in series with said common current source means and respective ones of said data gate means for gating current to respective ones of said data gate means for energizing same; and decoder means responsive to coded input signals to selectively energize respective ones of said current source gate means for selectively energizing respective ones of said data gate means for selectively gating respective data input signals onto said common output means.
Claim 2
Dependent Claim
127 words
In an emitter coupled logic transistor circuit: a common output means; a plurality of data gate means to which a plurality of respective data input signals are to be applied for gating onto said common output means; current source means common to said plurality of data gates for supplying current thereto; current source gate means connected in series with said common current source means and respective ones of said data gate means for gating current to respective ones of said data gate means for energizing same; and decoder means responsive to coded input signals to selectively energize respective ones of said current source gate means for selectively energizing respective ones of said data gate means for selectively gating respective data input signals onto said common output means.
Claim 3
Dependent Claim
101 words
The apparatus of claim 1 wherein said decoding means includes a plurality of multiple emitter transistor means, respective ones of said multiple emitter transistor means being connected with their multiple emitters to receive coded input signals for decoding same to derive respective true output signals when a plurality of said emitters have true inputs, means for connecting the output of respective ones of said multiple emitter transistor means to respective inputs of said current source gate means for gating open respective ones of said current source gate means in response to the respective true outputs of said multiple emitter transistor means.
Claim 4
Dependent Claim
41 words
The apparatus of claim 1 wherein respective ones of said data gate means include a pair of transistors having base, emitter and collector terminals, said transistors being connected with their collector-to-emitter terminals in parallel and with their emitter terminals connected together.
Claim 5
Dependent Claim
37 words
The apparatus of claim 3 wherein respective ones of said current source gate means are connected in series between said common current source means and said common emitter terminals of respective pairs of said data gate transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |