Master-slave flip-flop arrangement

Claim 2

In a clock-controlled storage arrangement of the type containing master and slave flip-flop storage elements each comprising, in upper and lower levels, series-coupled current switches, each having emitter-coupled transistors, and in which, in each storage element, a lower level clock-controlled current switch includes a transistor comprising a collector circuit, said collector circuit connected to an upper level current switch having a data input, the improvement therein comprising displacement means for displacing the switching thresholds of the storage elements including parallel-connected transistors in at least one of the lower current switches of the master and slave flip-flop storage elements, said displacement means comprising shift means connected to each of the lower current switches for providing shift-displaced control pulses including a plurality of parallel-connected transistors having common base, collector and emitter terminals and a diode-operating device connected in parallel with said common base and said common emitter terminals.

Claim 3

In the improved storage arrangement of claim 1, wherein said displacement means is further defined as comprising: response means for displacing the response threshold of the master flip-flop storage element.

Claim 4

In the improved storage arrangement of claim 1, wherein said displacement means is further defined as comprising: response means for displacing the response threshold of the slave flip-flop storage element.

Claim 5

In the improved storage arrangement of claim 1, wherein said displacement means is further defined as comprising: response means for displacing the response threshold of the master and slave flip-flop storage elements.

Claim 6

The improved storage arrangement of claim 1, wherein said displacement means is further defined as comprising: level displacement means for displacing the clock pulse level of the master flip-flop storage element.

Claim 7

The improved storage arrangement of claim 1, wherein said displacement means is further defined as comprising: level displacement means for displacing the clock pulse level of the slave flip-flop storage element.

Claim 8

The improved storage arrangement of claim 1, wherein said displacement means is further defined as comprising: level displacement means for displacing the clock pulse level of the master and slave flip-flop storage elements.

Claim 9

The improved storage arrangement of claim 1, wherein the upper and lower current switches of each flip-flop storage element have first and second current paths, and wherein said displacement means is further defined as comprising: parallel-connected transistors in said first current path in one of the flip-flop storage elements and parallel connected transistors in said second current path in the other of the flip-flop storage elements.

Claim 10

The improved circuit arrangement of claim 1, comprising: means connected to said lower current switches for deriving control pulses from the clock pulses including a plurality of diode-operating devices having a first terminal connected to one of the lower current switches and a second terminal connected to the other lower current switch to provide shift displaced control pulses, the lower current switches being connected to respective reference potentials.

Claim 11

The improved circuit arrangement of claim 1, comprising: means connected to and providing a first reference potential to one of the lower current switches including a constant current source, and a plurality of parallel connected transistors having a common base terminal connected to a first predetermined potential and a common emitter terminal connected to said constant current source and the lower current switch.

Claim 12

The improved circuit arrangement of claim 1, wherein said displacement means if further defined as comprising: means including parallel-connected transistors, connected to the lower current switch of one of the storage elements and operable to displace the switching threshold thereof; and means including parallel-connected diode-operating devices, connected to the lower current switch of the other storage element and operable to displace the level of the control pulses.

Claim 13

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop including a master data input for receiving input data, a clock input for receiving clock pulses and a master data output; a slave flip-flop including a slave data input connected to said master data output, a clock input connected in common with said clock input of said master flip-flop and a slave data output, said master and slave flip-flops each comprising first, second, third, fourth and fifth transistors each having a base, an emitter and a collector, and six and seventh transistors each having a base, an emitter, a collector and an additional electrode, and a constant current source, in said master flip-flop, said base of said first transistor connected to said master data input, said emitter connected to said emitter of said sixth transistor and said collector connected to a first potential, said collector of said sixth transistor connected to said master data output and to said base of said second transistor, said base of said sixth transistor connected to a second potential and said additional electrode connected to said base of said third transistor, said base of said second transistor and said collector of said third transistor together connected to the first potential via one of said resistors, and said emitters of said second and third transistors connected to said collectors of said fourth and seventh transistors, said emitters of said first and sixth transistors connected to said collector of said fifth transistor, and said emitters of said fourth, fifth and seventh transistors connected to a respective constant current source, said base of said fifth transistor connected to said clock input, and said additional electrode of said seventh transistor connected to said base of said fourth transistor and said base connected to a third potential, and in said slave flip-flop, said base of said first transistor connected to said slave data input, said emitter connected to said emitter of said sixth transistor and said collector connected to a first potential, said collector of said sixth transistor connected to said slave data output and to said base of said second transistor, said base of said sixth transistor connected to a second potential and said additional electrode connected to said base of said third transistor, said base of said second transistor and said collector of said third transistor connected to the first potential via another of said resistors, and said emitters of said second and third transistors connected to said collectors of said fourth and seventh transistors, said emitters of said first and sixth transistors connected to said collector of said fifth transistor, and said emitters of said fourth, fifth and seventh transistors connected to a respective constant current source, said base of said fifth transistor connected to said third potential, said additional electrode of said seventh transistor connected to said base of said fourth transistor and said base of said seventh transistor connected to said clock input, whereby the parallel connection of transistors provides a displacement of the switching thresholds.

Claim 14

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop including a master data input for receiving input data, a clock input for receiving clock pulses and a master data output; a slave flip-flop including a slave data input connected to said master data output, a clock input connected in common with said clock input of said master flip-flop and a slave data output, said master and slave flip-flops each comprising first, second, third, fourth and fifth transistors each having a base, an emitter and a collector, and six and seventh transistors each having a base, an emitter, a collector and an additional electrode, and a constant current source, in said master flip-flop, said base of said first transistor connected to said master data input, said emitter connected to said emitter of said sixth transistor and said collector connected to a first potential, said collector of said sixth transistor connected to said master data output and to said base of said second transistor, said base of said sixth transistor connected to a second potential and said additional electrode connected to said base of said third transistor, said base of said second transistor and said collector of said third transistor together connected to the first potential via one of said resistors, and said emitters of said second and third transistors connected to said collectors of said fourth and seventh transistors, said emitters of said first and sixth transistors connected to said collector of said fifth transistor, and said emitters of said fourth, fifth and seventh transistors connected to a respective constant current source, said base of said fifth transistor connected to said clock input, and said additional electrode of said seventh transistor connected to said base of said fourth transistor and said base connected to a third potential, and in said slave flip-flop, said base of said first transistor connected to said slave data input, said emitter connected to said emitter of said sixth transistor and said collector connected to a first potential, said collector of said sixth transistor connected to said slave data output and to said base of said second transistor, said base of said sixth transistor connected to a second potential and said additional electrode connected to said base of said third transistor, said base of said second transistor and said collector of said third transistor connected to the first potential via another of said resistors, and said emitters of said second and third transistors connected to said collectors of said fourth and seventh transistors, said emitters of said first and sixth transistors connected to said collector of said fifth transistor, and said emitters of said fourth, fifth and seventh transistors connected to a respective constant current source, said base of said fifth transistor connected to said third potential, said additional electrode of said seventh transistor connected to said base of said fourth transistor and said base of said seventh transistor connected to said clock input, whereby the parallel connection of transistors provides a displacement of the switching thresholds.

Claim 15

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop and a slave flip-flop including a master data input, a master data output, a slave data input connected to said master data output, a slave data output, a master clock input and a slave clock input, each of said flip-flops comprising first, second, third, fourth, fifth and sixth transistors each including a base, a collector and an emitter with said bases of said second and third transistors being common thereto and said collectors of said second and third transistors being common thereto, said base of said first transistor connected to the respective data input, said collector of said first transistor connected to a first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said fifth transistor, said common collector of said second and third transistors connected to said base of said fourth transistor, to the respective data output and via one of said resistors to the first potential, said base of said second transistor connected to a second potential, said collector of said fourth transistor connected to the first potential and said emitters of said third and fourth transistors connected to said collector of said sixth transistor, said emitters of said fifth and sixth transistors connected to a third potential via a respective one of said constant current sources, said base of said sixth transistor of said master flip-flop connected to a fourth potential and said base of said fifth transistor of said master flip-flop constituting said master clock input, said base of said fifth transistor of said slave flip-flop connected to a fifth potential an said base of said sixth transistor of said slave flip-flop constituting said slave clock input; and clock means including a clock input for receiving clock pulses, a master clock output connected to said master clock input and a slave clock output connected to said slave clock input, said clock means including means connected between said clock input and said master an slave clock outputs and responsive to an input clock pulse to provide master clock pulses of a first magnitude and slave clock pulses of a second magnitude.

Claim 16

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop and a slave flip-flop including a master data input, a master data output, a slave data input connected to said master data output, a slave data output, a master clock input and a slave clock input, each of said flip-flops comprising first, second, third, fourth, fifth and sixth transistors each including a base, a collector and an emitter with said bases of said second and third transistors being common thereto and said collectors of said second and third transistors being common thereto, said base of said first transistor connected to the respective data input, said collector of said first transistor connected to a first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said fifth transistor, said common collector of said second and third transistors connected to said base of said fourth transistor, to the respective data output and via one of said resistors to the first potential, said base of said second transistor connected to a second potential, said collector of said fourth transistor connected to the first potential and said emitters of said third and fourth transistors connected to said collector of said sixth transistor, said emitters of said fifth and sixth transistors connected to a third potential via a respective one of said constant current sources, said base of said sixth transistor of said master flip-flop connected to a fourth potential and said base of said fifth transistor of said master flip-flop constituting said master clock input, said base of said fifth transistor of said slave flip-flop connected to a fifth potential an said base of said sixth transistor of said slave flip-flop constituting said slave clock input; and clock means including a clock input for receiving clock pulses, a master clock output connected to said master clock input and a slave clock output connected to said slave clock input, said clock means including means connected between said clock input and said master an slave clock outputs and responsive to an input clock pulse to provide master clock pulses of a first magnitude and slave clock pulses of a second magnitude.

Claim 17

The clock-controlled data storage arrangement of claim 13, wherein said clock means is further defined as comprising: a clock input transistor including a base for receiving clock pulses, and a collector-emitter circuit connected in series with one of said constant current sources between the first and third potentials; and a plurality of parallel-connected semiconductor elements connected in series between said transistor and said constant current source and including said master and slave clock outputs.

Claim 18

The clock-controlled data storage arrangement of claim 14, wherein said plurality of semiconductor elements comprises: a plurality of parallel-connected semiconductor devices connected to operate as diodes, the commonly-connected terminals of said diodes constituting said master and slave clock outputs.

Claim 19

The clock-controlled data storage arrangement of claim 14, wherein said plurality of semiconductor elements comprises: a plurality of parallel-connected transistors connected to operate as diodes.

Claim 20

The clock-controlled data storage arrangement of claim 14, wherein said plurality of semiconductor elements comprises: a plurality of transistors having a common base terminal connected to said collector-emitter circuit, a common collector terminal connected to the first potential and a common emitter terminal connected as and constituting said slave clock output; and a diode-operating element serially connected between said collector-emitter circuit and said one constant current source and connected to provide said master clock output.

Claim 21

The clock-controlled data storage arrangement of claim 13, wherein: in said slave flip-flop, said sixth transistor has a seventh transistor connected thereto, said seventh transistor including a base in common with said base of said sixth transistor, a collector in common with said collector of said sixth transistor, and an emitter in common with said emitter of said sixth transistor.

Claim 22

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop and a slave flip-flop including a master data input, a master data output, a slave data input connected to said master data output, a slave data output, a master clock input, and a slave clock input connected to said master clock input, each of said flip-flops comprising first, second, third, fourth, fifth and sixth transistors each including a base, a collector and an emitter with said bases of said second and third transistors being common thereto and said collectors of said second and third transistors being common thereto, said base of said first transistor connected to the respective data input, said collector of said first transistor connected to a first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said fifth transistor, said collector of said second transistor connected to said base of said fourth transistor, to the respective data output and to the first potential, and said base of said second transistor connected to a second potential, said collector of said fourth transistor and said common collectors of said second and third transistors connected to the first potential via one of said resistors, and said emitters of said third and fourth transistors connected to said collector of said sixth transistor, said emitters of said fifth and sixth transistors connected to a third potential via a respective on of said constant current sources, said base of said fifth transistor of said master flip-flop and said base of said sixth transistor of said slave flip-flop connected as said master and slave clock inputs, said base of said fifth transistor of said slave flip-flop connected to a fourth potential, and said base of said sixth transistor of said master flip-flop connected to a fifth potential; and means for deriving the fifth potential from the first, second and third potentials comprising a plurality of parallel-connected transistors having a common base terminal connected to the second potential, a common collector terminal connected to the first potential and a common emitter terminal connected via one of said constant current sources to the third potential.

Claim 23

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop and a slave flip-flop including a master data input, a master data output, a slave data input connected to said master data output, a slave data output, a master clock input, and a slave clock input connected to said master clock input, each of said flip-flops comprising first, second, third, fourth, fifth and sixth transistors each including a base, a collector and an emitter with said bases of said second and third transistors being common thereto and said collectors of said second and third transistors being common thereto, said base of said first transistor connected to the respective data input, said collector of said first transistor connected to a first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said fifth transistor, said collector of said second transistor connected to said base of said fourth transistor, to the respective data output and to the first potential, and said base of said second transistor connected to a second potential, said collector of said fourth transistor and said common collectors of said second and third transistors connected to the first potential via one of said resistors, and said emitters of said third and fourth transistors connected to said collector of said sixth transistor, said emitters of said fifth and sixth transistors connected to a third potential via a respective on of said constant current sources, said base of said fifth transistor of said master flip-flop and said base of said sixth transistor of said slave flip-flop connected as said master and slave clock inputs, said base of said fifth transistor of said slave flip-flop connected to a fourth potential, and said base of said sixth transistor of said master flip-flop connected to a fifth potential; and means for deriving the fifth potential from the first, second and third potentials comprising a plurality of parallel-connected transistors having a common base terminal connected to the second potential, a common collector terminal connected to the first potential and a common emitter terminal connected via one of said constant current sources to the third potential.

Claim 24

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop and a slave flip-flop including a master data input, a master data output, a slave data input connected to said master data output, a slave data output, a master clock input and a slave clock input connected to said master clock input forming a common clock input, each of said flip-flops comprising first, second, third, fourth, fifth, sixth and seventh transistors each including a base, a collector and an emitter with the bases of said second and third transistors being common thereto, said collectors of said second and third transistors being common thereto and connected to a first potential via a respective resistor in each flip-flop, said base of said sixth and seventh transistors in common thereto in said slave flip-flop, said bases of said fifth and seventh transistors common thereto in said master flip-flop, said collectors of said sixth and seventh transistors common thereto in said slave flip-flop, said collectors of said sixth and seventh transistors common thereto in said master flip-flop, and said emitters of said fifth, sixth an seventh transistors connected in common in both flip-flops, said base of said first transistor connected to the respective data input, said collector of said first transistor connected to the first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said fifth transistor in said slave flip-flop, and said collector of said first transistor connected to the first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said sixth transistor in said master flip-flop, said collector of said second and third transistors connected to said base of said fourth transistor, to the respective data output and to the first potential, and said base of said second transistor connected to a second potential in both flip-flops, said collector of said fourth transistor connected to the first potential and said emitters of said third and fourth transistors connected to said collector of said sixth transistor in said slave flip-flop, and said emitters of said third and fourth transistors connected to said collector of said fifth transistor in said master flip-flop, said emitters of said fifth, sixth and seventh transistors connected to a third potential via a respective one of said constant current sources in both flip-flops, and said base of said sixth transistor of each of said master and slave flip-flops connected to a fourth potential, and said base of said fifth transistor in both said master and slave flip-flops connected to said common clock input.

Claim 25

A clock-controlled data storage arrangement comprising: a plurality of constant current sources; a plurality of resistors; a master flip-flop and a slave flip-flop including a master data input, a master data output, a slave data input connected to said master data output, a slave data output, a master clock input and a slave clock input connected to said master clock input forming a common clock input, each of said flip-flops comprising first, second, third, fourth, fifth, sixth and seventh transistors each including a base, a collector and an emitter with the bases of said second and third transistors being common thereto, said collectors of said second and third transistors being common thereto and connected to a first potential via a respective resistor in each flip-flop, said base of said sixth and seventh transistors in common thereto in said slave flip-flop, said bases of said fifth and seventh transistors common thereto in said master flip-flop, said collectors of said sixth and seventh transistors common thereto in said slave flip-flop, said collectors of said sixth and seventh transistors common thereto in said master flip-flop, and said emitters of said fifth, sixth an seventh transistors connected in common in both flip-flops, said base of said first transistor connected to the respective data input, said collector of said first transistor connected to the first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said fifth transistor in said slave flip-flop, and said collector of said first transistor connected to the first potential and said emitter of said first transistor connected to said emitter of said second transistor and to said collector of said sixth transistor in said master flip-flop, said collector of said second and third transistors connected to said base of said fourth transistor, to the respective data output and to the first potential, and said base of said second transistor connected to a second potential in both flip-flops, said collector of said fourth transistor connected to the first potential and said emitters of said third and fourth transistors connected to said collector of said sixth transistor in said slave flip-flop, and said emitters of said third and fourth transistors connected to said collector of said fifth transistor in said master flip-flop, said emitters of said fifth, sixth and seventh transistors connected to a third potential via a respective one of said constant current sources in both flip-flops, and said base of said sixth transistor of each of said master and slave flip-flops connected to a fourth potential, and said base of said fifth transistor in both said master and slave flip-flops connected to said common clock input.