US4289979A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistorized master slave flip-flop having threshold offsets generated by circuit size variations
Assignee: Unisys Corp
•
Filing: 1978-08-28
•
Granted: 1981-09-15
•
Expires: 1998-08-28
Abstract
Abstract A transistorized master slave flip-flop having a threshold offset generated through circuit size variations. The area of the emitter regions of selected bipolar transistors in the master and slave flip-flops are varied to provide preferred sequencing and thereby avoid untimely changes in state. Adjusting the area of the emitter regions provides the necessary offset without increasing the number of components or circuit crossovers.
Inventors
- 👤 Harold Muller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:30
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
458 words
A master slave flip-flop circuit comprising: input signal source means; a master flip-flop coupled to said input signal source means and having a data intake circuit for passing the input source signal to the output of said master flip-flop and a latch circuit for preventing the input source signal from being passed through the output of said master flip-flop; a slave flip-flop coupled to said master flip-flop and to said input signal source means, said slave flip-flop having a data intake circuit for passing the signal of said input signal source means to the output of said slave flip-flop and a latch circuit for preventing the signal from said input signal source means from being passed to the output said slave flip-flop; and means for actuating the data intake circuit and the latch circuit of said master flip-flop and the data intake circuit and the latch circuit of said slave flip-flop such that the data intake circuit of said master flip-flop and the data intake circuit of said slave flip-flop are never simultaneously actuated; said means for actuating the data intake circuit and the latch circuit of the master flip-flop comprising: a source of clock signals; a first current source; a first multi-emitter bipolar transistor having its base coupled to said source of clock signals, its emitters coupled to said first current source and its collector coupled to said data intake circuit of said master flip-flop; a DC voltage source having a constant output intermediate the voltage range of said clock signals; and a first bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said latch circuit of said master flip-flop and its emitter coupled to said first current source whereby current from said current source is steered by said first bipolar transistor to said latch circuit of said master flip-flop when the level of said clock signal is less than said voltage level of said first DC voltage source and where said current from said first current source is steered through said first multi-emitter transistor to said data intake circuit of said master flip-flop when said voltage level of said clock signal is greater than said voltage level of said constant DC voltage source; said means for actuating the data intake circuit and the latch circuit of said slave flip-flop comprising: a second current source; a second multi-emitter bipolar transistor having its base coupled to said source of clock signals, its collector coupled to said latch circuit and its emitters coupled to said second current source; and a second bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said data intake circuit of said slave flip-flop and its emitter coupled to said second current source.
Claim 2
Dependent Claim
458 words
A master slave flip-flop circuit comprising: input signal source means; a master flip-flop coupled to said input signal source means and having a data intake circuit for passing the input source signal to the output of said master flip-flop and a latch circuit for preventing the input source signal from being passed through the output of said master flip-flop; a slave flip-flop coupled to said master flip-flop and to said input signal source means, said slave flip-flop having a data intake circuit for passing the signal of said input signal source means to the output of said slave flip-flop and a latch circuit for preventing the signal from said input signal source means from being passed to the output said slave flip-flop; and means for actuating the data intake circuit and the latch circuit of said master flip-flop and the data intake circuit and the latch circuit of said slave flip-flop such that the data intake circuit of said master flip-flop and the data intake circuit of said slave flip-flop are never simultaneously actuated; said means for actuating the data intake circuit and the latch circuit of the master flip-flop comprising: a source of clock signals; a first current source; a first multi-emitter bipolar transistor having its base coupled to said source of clock signals, its emitters coupled to said first current source and its collector coupled to said data intake circuit of said master flip-flop; a DC voltage source having a constant output intermediate the voltage range of said clock signals; and a first bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said latch circuit of said master flip-flop and its emitter coupled to said first current source whereby current from said current source is steered by said first bipolar transistor to said latch circuit of said master flip-flop when the level of said clock signal is less than said voltage level of said first DC voltage source and where said current from said first current source is steered through said first multi-emitter transistor to said data intake circuit of said master flip-flop when said voltage level of said clock signal is greater than said voltage level of said constant DC voltage source; said means for actuating the data intake circuit and the latch circuit of said slave flip-flop comprising: a second current source; a second multi-emitter bipolar transistor having its base coupled to said source of clock signals, its collector coupled to said latch circuit and its emitters coupled to said second current source; and a second bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said data intake circuit of said slave flip-flop and its emitter coupled to said second current source.
Claim 3
Dependent Claim
217 words
A master slave flip-flop circuit for actuating an output signal means in response to an input signal comprising: a source of clock signals; an input signal source; a master flip-flop for coupling said input signal to said output signal means; a slave flip-flop for coupling said input signal to said output signal means; current steering means for actuating said master flip-flop to couple said input signal to said output signal means during a first portion of each of said clock signals and for preventing the coupling of said input signal to said output signal means through said master flip-flop during a second portion of each of said clock signals and for actuating said slave flip-flop to couple said input signal to said output signal means during each of said second portions of said clock signals and for preventing said slave flip-flop from coupling said input signal to said output signal means during each of said first portions of said clock signals; wherein said current steering means steers current from said first current source through said data intake circuit of said master flip-flop during said first portion of said clock signals and steers the current from said first current source through said latch circuit of said master flip-flop during said second and third portions of said clock signals.
Claim 4
Dependent Claim
217 words
A master slave flip-flop circuit for actuating an output signal means in response to an input signal comprising: a source of clock signals; an input signal source; a master flip-flop for coupling said input signal to said output signal means; a slave flip-flop for coupling said input signal to said output signal means; current steering means for actuating said master flip-flop to couple said input signal to said output signal means during a first portion of each of said clock signals and for preventing the coupling of said input signal to said output signal means through said master flip-flop during a second portion of each of said clock signals and for actuating said slave flip-flop to couple said input signal to said output signal means during each of said second portions of said clock signals and for preventing said slave flip-flop from coupling said input signal to said output signal means during each of said first portions of said clock signals; wherein said current steering means steers current from said first current source through said data intake circuit of said master flip-flop during said first portion of said clock signals and steers the current from said first current source through said latch circuit of said master flip-flop during said second and third portions of said clock signals.
Claim 5
Dependent Claim
40 words
The master slave flip-flop of claim 2 wherein said current steering means prevents both master flip-flop and said slave flip-flop from coupling said input signal to said output signal means during a third portion of each of said clock signals.
Claim 6
Dependent Claim
33 words
The master slave flip-flop of claim 3 wherein said master flip-flop comprises a data intake circuit and a latch circuit and said slave flip-flop comprises a data intake circuit and a latch circuit.
Claim 7
Dependent Claim
28 words
A master slave flip-flop of claim 4 further including a first current source associated with said master flip-flop and a second current source associated with said slave flip-flop.
Claim 8
Dependent Claim
58 words
The master slave flip-flop of claim 5 wherein said current steering means steers current through the data intake circuit of said slave flip-flop during said second portion of said clock signal and steers said current from said second current source through said latch circuit of said slave flip-flop during said first and third portions of said clock signal.
Claim 9
Dependent Claim
152 words
The master slave flip-flop of claim 6 wherein said current steering means comprises: a first multi-emitter transistor having its base coupled to said source of clock signals, its emitters coupled to said first current source and its collector coupled to said data intake circuit of said master flip-flop; a first bipolar transistor having its base coupled to said constant DC voltage source, its collector coupled to said latch circuit of said master flip-flop and its emitter coupled to said first current source; a second multi-emitter transistor having its base coupled to said source of clock signals, its collector coupled to the latch circuit of said slave flip-flop and its emitters coupled to said second current source; and a second bipolar transistor having its base coupled to said constant DC voltage source, its collector coupled to said data intake circuit of said slave flip-flop and its emitter coupled to said second current source.
Claim 10
Dependent Claim
342 words
A circuit for inhibiting erroneous changes of state in a master slave flip-flop comprising: a source of clock signals; a source of input signals; a master flip-flop having a data intake circuit and a latch circuit; means comprising a first current source, a first multi-emitter bipolar transistor having its base coupled to said source of clock signals, its emitters coupled to said first current source and its collector coupled to said data intake circuit of said master flip-flop; a DC voltage source having a constant output intermediate the voltage range of said clock signals; and a first bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said latch circuit of said master flip-flop and its emitter coupled to said first current source, for generating a switching voltage differential in said master flip-flop such that said data intake circuit of said master flip-flop is actuated only during a first portion of each of said clock signals and said latch circuit of said master flip-flop is actuated only during a second portion and a third portion of each of said clock signals; a slave flip-flop having a data intake circuit and a latch circuit; means comprising a second current source, a second multi-emitter bipolar transistor having its base coupled to said source of clock signals, its collector coupled to said latch circuit of said slave flip-flop and its emitters coupled to second current source, a second bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said data intake circuit of said slave flip-flop and its emitter coupled to said second current source for actuating said data intake circuit of said slave flip-flop only during said second portion of each of said clock signals and for actuating said latch circuit of said slave flip-flop only during said first portion and said third portion of each of said clock signals whereby the data intake circuit of said master flip-flop and the data intake circuit of said slave flip-flop are inhibited from being simultaneously actuated.
Claim 11
Dependent Claim
342 words
A circuit for inhibiting erroneous changes of state in a master slave flip-flop comprising: a source of clock signals; a source of input signals; a master flip-flop having a data intake circuit and a latch circuit; means comprising a first current source, a first multi-emitter bipolar transistor having its base coupled to said source of clock signals, its emitters coupled to said first current source and its collector coupled to said data intake circuit of said master flip-flop; a DC voltage source having a constant output intermediate the voltage range of said clock signals; and a first bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said latch circuit of said master flip-flop and its emitter coupled to said first current source, for generating a switching voltage differential in said master flip-flop such that said data intake circuit of said master flip-flop is actuated only during a first portion of each of said clock signals and said latch circuit of said master flip-flop is actuated only during a second portion and a third portion of each of said clock signals; a slave flip-flop having a data intake circuit and a latch circuit; means comprising a second current source, a second multi-emitter bipolar transistor having its base coupled to said source of clock signals, its collector coupled to said latch circuit of said slave flip-flop and its emitters coupled to second current source, a second bipolar transistor having its base coupled to said DC voltage source, its collector coupled to said data intake circuit of said slave flip-flop and its emitter coupled to said second current source for actuating said data intake circuit of said slave flip-flop only during said second portion of each of said clock signals and for actuating said latch circuit of said slave flip-flop only during said first portion and said third portion of each of said clock signals whereby the data intake circuit of said master flip-flop and the data intake circuit of said slave flip-flop are inhibited from being simultaneously actuated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-14 | 1985-03-16 | 1985-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-14 | 1989-03-16 | 1989-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-14 | 1993-03-16 | 1993-09-15 | $7700.00 | Window Closed / Lapsed |