US5144174A
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Programmable delay circuit having a buffer stage connected in cascode between the outputs of a plurality of differential amplifiers and the output terminal
Abstract A programmable delay circuit of the present invention is comprised of an input terminal to which an input signal to be delayed is supplied, N (N≧2) delay circuits of a plurality of stages connected in cascade, a plurality of differential amplifier transistors connected to respective stages between the delay circuits of the plurality of stages and having a pair of differential amplifier transistors and current switches for supplying a drive current from a common current source to the pair of differential amplifier transistors, a common output terminal commonly connected to respective outputs of a pair of differential amplifier transistors of the plurality of differential amplifiers and a control circuit for selectively controlling the current switches of the plurality of differential amplifiers, wherein even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced. When a buffer stage connected in cascode is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced and thus the programmable delay circuit of the present invention can be operated at high speed.
A programmable delay circuit comprising: (a) an input terminal to which an input signal to be delayed is supplied; (b) N (N≧2) delay circuits of a plurality of stages connected in cascade; (c) a plurality of differential amplifiers respectively connected to respective stages between said plurality of stages of delay circuits and having a pair of differential amplifier transistors and current switches for supplying a drive current from a common current source to said pair of differential amplifier transistors; (d) an output terminal commonly coupled to respective output terminals of said pair of differential amplifier transistors of said plurality of differential amplifiers; (e) a buffer stage connected in cascode between said respective output terminals of aid plurality of differential amplifiers and said common output terminal; and (f) a digital control circuit for selecting only one of said current switches of said plurality of differential amplifiers.
Claim 2
Dependent Claim
145 words
A programmable delay circuit comprising: (a) an input terminal to which an input signal to be delayed is supplied; (b) N (N≧2) delay circuits of a plurality of stages connected in cascade; (c) a plurality of differential amplifiers respectively connected to respective stages between said plurality of stages of delay circuits and having a pair of differential amplifier transistors and current switches for supplying a drive current from a common current source to said pair of differential amplifier transistors; (d) an output terminal commonly coupled to respective output terminals of said pair of differential amplifier transistors of said plurality of differential amplifiers; (e) a buffer stage connected in cascode between said respective output terminals of aid plurality of differential amplifiers and said common output terminal; and (f) a digital control circuit for selecting only one of said current switches of said plurality of differential amplifiers.
Claim 3
Dependent Claim
29 words
A programmable delay circuit according to claim 1, wherein a buffer stage connected in cascode is provided between outputs of said plurality of differential amplifiers and said output terminal.
Claim 4
Dependent Claim
22 words
A programmable delay circuit according to claim 2, wherein the input signal to be delayed is directly supplied to said output terminal.
Claim 5
Dependent Claim
36 words
A programmable delay circuit according to claim 3, wherein an emitter-follower stage is connected between the input terminal to which the input signal to be delayed is supplied and the delay circuit of the first stage.
Claim 6
Dependent Claim
44 words
A programmable delay circuit according to claim 4, wherein a push-pull signal is supplied to said input terminal to which the input signal to be delayed is supplied and a push-pull signal delayed by a predetermined delay time is developed at said output terminal.