Method for providing a delayed signal and controllable delay circuit

Claim 3

A method according to claim 1, wherein the step of combining said first and additional ampli­fier outputs comprises the step of summing the first and additional amplifier outputs.

Claim 6

A method according to claim 3, wherein the step of adjusting a delay comprises: adjusting at least one and not more than two of said first and additional amplifiers for non-zero gain; and adjusting all others of said first and additional amplifiers for zero gain.

Claim 7

A method according to claim 3, wherein the step of combining said first and additional amplifier outputs comprises the step of summing the first and additional amplifier outputs.

Claim 8

A delay circuit for producing an output signal that changes state in delayed response to a change in state of an input signal, the delay circuit comprising: means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the input signal; first amplification means for receiving the input signal as input and providing a first amplifier output; a plurality of additional amplification means, each corresponding to a separate one of said plurality of delayed signals, each additional amplification means receiving its corresponding delayed signal as input and providing a separate additional amplifier output; and means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

Claim 9

A delay circuit for producing an output signal that changes state in delayed response to a change in state of an input signal, the delay circuit comprising: means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the input signal; first amplification means for receiving the input signal as input and providing a first amplifier output; a plurality of additional amplification means, each corresponding to a separate one of said plurality of delayed signals, each additional amplification means receiving its corresponding delayed signal as input and providing a separate additional amplifier output; and means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

Claim 10

A delay circuit according to claim 6, wherein the means for combining the first amplifier output and the additional amplifier outputs com­prises means for summing the first amplifier output and the additional amplifier outputs.

Claim 11

A delay circuit for producing a delay circuit output signal that changes state in adjustably delayed response to a change in state of an input signal, the delay circuit comprising: means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the input signal; first amplification means having variable gain for receiving the input signal as input and providing a first amplifier output; a plurality of additional amplification means, each having variable gain, each corresponding to a separate one of said plurality of delayed signals, and each receiving its corresponding delayed signal as input and providing a separate additional amplifier output; means for controlling the gains of said first amplification means and said additional amplification means; and means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

Claim 12

A delay circuit for producing a delay circuit output signal that changes state in adjustably delayed response to a change in state of an input signal, the delay circuit comprising: means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the input signal; first amplification means having variable gain for receiving the input signal as input and providing a first amplifier output; a plurality of additional amplification means, each having variable gain, each corresponding to a separate one of said plurality of delayed signals, and each receiving its corresponding delayed signal as input and providing a separate additional amplifier output; means for controlling the gains of said first amplification means and said additional amplification means; and means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

Claim 13

A delay circuit according to claim 8, wherein the means for combining the first amplifier output and the additional amplifier outputs com­prises means for summing the first amplifier output and the additional amplifier outputs to provide the delay circuit output signal.

Claim 14

A delay circuit responsive to a control signal for producing a delay circuit output signal that changes state in adjustably delayed response to a change in state of a delay circuit input signal, the delay circuit comprising: means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the delay circuit input signal; a first amplifier having a variable gain controlled by a first gain control current applied thereto, for receiving the delay circuit input signal as input and providing a first differential current output, said first amplifier comprising: a first transistor having a first terminal, a second terminal, and a third terminal; and a second transistor having a first terminal, a second terminal, and a third terminal, the delay circuit input signal being applied across the first terminal of the first transistor and the first terminal of the second transistor, the second ter­minal of the first transistor being coupled to the second terminal of the second tran­sistor and receiving said first gain con­trol current, and the first differential current output being provided by the third terminal of the first transistor and the third terminal second transistor; a plurality of additional amplifiers each corresponding to a separate one of said plurality of delayed signals and each having a variable gain controlled by a separate one of a plurality of additional gain control currents, each of said additional amplifiers receiving its corresponding delayed signal as input and providing a separate differential current additional amplifier output, each of said additional amplifiers comprising: a third transistor having a first terminal, a second terminal, and a third terminal; and a fourth transistor having a first terminal, a second terminal, and a third terminal, the corresponding delayed signal being applied across the first terminal of the third transistor and the first ter­minal of the fourth transistor, the second terminal of the third transistor being coupled to the second terminal of the fourth transistor and receiving one of said additional gain control currents, and the additional amplifier output signal being provided at the third terminal of the third transistor and the third ter­minal fourth transistor; means for supplying said first and addi­tional gain control currents of adjustable magni­tude to said first and additional amplifiers in accordance with a magnitude of said control signal; and means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

Claim 15

A delay circuit responsive to a control signal for producing a delay circuit output signal that changes state in adjustably delayed response to a change in state of a delay circuit input signal, the delay circuit comprising: means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the delay circuit input signal; a first amplifier having a variable gain controlled by a first gain control current applied thereto, for receiving the delay circuit input signal as input and providing a first differential current output, said first amplifier comprising: a first transistor having a first terminal, a second terminal, and a third terminal; and a second transistor having a first terminal, a second terminal, and a third terminal, the delay circuit input signal being applied across the first terminal of the first transistor and the first terminal of the second transistor, the second ter­minal of the first transistor being coupled to the second terminal of the second tran­sistor and receiving said first gain con­trol current, and the first differential current output being provided by the third terminal of the first transistor and the third terminal second transistor; a plurality of additional amplifiers each corresponding to a separate one of said plurality of delayed signals and each having a variable gain controlled by a separate one of a plurality of additional gain control currents, each of said additional amplifiers receiving its corresponding delayed signal as input and providing a separate differential current additional amplifier output, each of said additional amplifiers comprising: a third transistor having a first terminal, a second terminal, and a third terminal; and a fourth transistor having a first terminal, a second terminal, and a third terminal, the corresponding delayed signal being applied across the first terminal of the third transistor and the first ter­minal of the fourth transistor, the second terminal of the third transistor being coupled to the second terminal of the fourth transistor and receiving one of said additional gain control currents, and the additional amplifier output signal being provided at the third terminal of the third transistor and the third ter­minal fourth transistor; means for supplying said first and addi­tional gain control currents of adjustable magni­tude to said first and additional amplifiers in accordance with a magnitude of said control signal; and means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

Claim 16

A delay circuit according to claim 10, wherein said means for supplying said gain control currents comprises: a first current source for providing a first current; and means for selectively dividing the first current in accordance with said control signal to provide said first gain control current and said plurality of additional gain control currents.

Claim 17

A delay circuit according to claim 11, wherein said means for selectively dividing the first current comprises: a plurality of gain control transistors each corresponding to a separate one of the first and additional gain control currents, each gain control transistor having a first terminal, a second terminal coupled to said first current source, and a third terminal for providing one of said first and additional gain control currents; and means for adjusting control voltages between the first terminals of pairs of said gain control transistors, said control voltages being adjusted in accordance with the magnitude of said control signal such that at least one and not more than two gain control currents have non-zero magnitudes.

Claim 18

A delay circuit according to claim 12, wherein said means for adjusting control voltages comprises: a plurality of resistors connected in series, each resistor also being connected between the third terminals of a corresponding pair of said gain control transistors; a plurality of current sources, each con­nected to the first terminal of a separate one of said gain control transistors; and a control amplifier responsive to said control signal for producing a differential control current supplied to said series of resistors such that said adjustable voltages are developed across said resistors in accordance with the magnitude of said control signal.