Integrated circuit degradation resistant structure

Claim 2

An integrated circuit having a plurality of transistors selectively formed to reduce hot-electron-induced degradation of gates of selected ones of said plurality of transistors, said integrated circuit comprising: a substrate having a first group of regions and a second group of regions, said second group of regions for forming said selectively formed transistors for reduced hot-electron-induced degradation of gates; each one of said first group of regions including a transistor having an oxide spacer positioned adjacent its gate; and each one of said second group of regions including a transistor having both a polysilicon spacer positioned adjacent its gate, and an oxide spacer formed adjacent said polysilicon spacer such that said polysilicon spacer is located between said gate and said oxide spacer for reducing hot-electron-induced degradation of its gate.

Claim 3

The integrated circuit of claim 1 wherein each of said transistors of said first and second groups of regions are formed over a substrate having a channel region between a source region and a drain region and having said gage overlying said channel region and separated therefrom by a gate oxide layer, an oxide cover layer formed over said gate, including the side walls of said gate, and in contact with said gate oxide layer; and each of said transistors of said second group of regions further including said polysilicon spacer formed between said oxide cover layer and said oxide spacer so as to be substantially enclosed.

Claim 4

An integrated circuit having a first group of transistors and a second group of transistors, said second group of transistor shaving increased resistance to hot-electron-induced degradation, said integrated circuit comprising: a substrate having first regions for forming said first group of transistors therein, and second regions for forming said second group of transistors therein; each transistor of said first and second groups defining a channel region between a source region and a drain region and having a gate overlying said channel region, said gate separated from said channel region by a gate oxide; an oxide cover layer formed over said first and second groups of transistors, including said source and drain regions and the sidewalls of said gates, said oxide cover layer in contact with said gate oxide layer; each one of said first group of transistors including an oxide spacer formed adjacent and in contact with said oxide cover layer where said cover layer covers said sidewalls of the gate; and each one of said second group of transistors including a polysilicon spacer formed adjacent and in contact with said oxide cover layer where said cover layer covers said sidewalls of the gate, and each one of said second group of transistors further including an oxide spacer formed adjacent and in contact with said polysilicon spacer and in contact with said oxide cover layer where said cover layer is formed over said source and drain regions.

Claim 5

An integrated circuit having a first group of transistors and a second group of transistors, said second group of transistor shaving increased resistance to hot-electron-induced degradation, said integrated circuit comprising: a substrate having first regions for forming said first group of transistors therein, and second regions for forming said second group of transistors therein; each transistor of said first and second groups defining a channel region between a source region and a drain region and having a gate overlying said channel region, said gate separated from said channel region by a gate oxide; an oxide cover layer formed over said first and second groups of transistors, including said source and drain regions and the sidewalls of said gates, said oxide cover layer in contact with said gate oxide layer; each one of said first group of transistors including an oxide spacer formed adjacent and in contact with said oxide cover layer where said cover layer covers said sidewalls of the gate; and each one of said second group of transistors including a polysilicon spacer formed adjacent and in contact with said oxide cover layer where said cover layer covers said sidewalls of the gate, and each one of said second group of transistors further including an oxide spacer formed adjacent and in contact with said polysilicon spacer and in contact with said oxide cover layer where said cover layer is formed over said source and drain regions.

Claim 6

The integrated circuit as recited in claim 3 wherein said oxide cover layer is approximately 100 Angstroms thick.

Claim 7

The integrated circuit as recited in claim 3 wherein said polysilicon spacer is formed from a polysilicon layer approximately 1200 Angstroms thick.

Claim 8

The integrated circuit as recited in claim 3 wherein said oxide spacer of said first and second groups of transistors, is formed from an oxide layer approximately 1200 Angstroms thick.

Claim 9

The integrated circuit of claim 3 wherein said polysilicon spacer is substantially enclosed by said oxide spacer and said oxide cover layer.