Insulated gate type semiconductor device and method of manufacturing the same

Claim 2

A logic circuit for an insulated gate type semiconductor device, comprising: input terminal means for receiving an input signal; output terminal means for supplying an output signal having a logic value determined by said input signal; a first N channel transistor directly connected to said output terminal means and having source, drain and channel regions, said drain region including a high-impurity concentration region and a low-impurity concentration region located contiguous to said channel region, and said source region including a high-impurity concentration region contiguous to said channel region; a second N channel transistor connected between said first N channel transistor and a low potential, and having source, drain and channel regions, said drain and source regions each including high-impurity concentration regions located contiguous to said channel region; and a load transistor connected between said output terminal means and a high potential.

Claim 3

A logic circuit for an insulated gate type semiconductor device according to claim 1, wherein said high-impurity concentration is higher than about 10 20 cm -3 , and said low-impurity concentration is lower than about 5×10 18 cm -3 .

Claim 4

A logic circuit for an insulated gate type semiconductor device, comprising: input terminal means for receiving an input signal; output terminal means for supplying an output signal having a logic value determined by said input signal; a first N channel transistor directly connected to said output terminal means and having source, drain and channel regions, said drain region including a high-impurity concentration region and a low-impurity concentration region located contiguous to said channel region, and said source region including a high-impurity concentration region contiguous to said channel region; a second N channel transistor connected between said first N channel transistor and a low potential, and having source, drain and channel regions, said drain and source regions each including high-impurity concentration regions located contiguous to said channel region; a third N channel transistor connected between said second N channel transistor and said low potential, and having source, drain and channel regions, said drain and source regions of said third transistor including high-impurity concentration regions located contiguous to said channel region; and a load transistor connected between said output terminal means and a high potential.

Claim 5

A logic circuit for an insulated gate type semiconductor device, comprising: input terminal means for receiving an input signal; output terminal means for supplying an output signal having a logic value determined by said input signal; a first N channel transistor directly connected to said output terminal means and having source, drain and channel regions, said drain region including a high-impurity concentration region and a low-impurity concentration region located contiguous to said channel region, and said source region including a high-impurity concentration region contiguous to said channel region; a second N channel transistor connected between said first N channel transistor and a low potential, and having source, drain and channel regions, said drain and source regions each including high-impurity concentration regions located contiguous to said channel region; a third N channel transistor connected between said second N channel transistor and said low potential, and having source, drain and channel regions, said drain and source regions of said third transistor including high-impurity concentration regions located contiguous to said channel region; and a load transistor connected between said output terminal means and a high potential.

Claim 6

A logic circuit for an insulated gate type semiconductor device according to claim 3, wherein said high-impurity concentration is higher than about 10 20 cm -3 , and said low-impurity concentration is lower than about 5×10 18 cm -3 .

Claim 7

A logic circuit for an insulated gate type semiconductor device, comprising: input terminal means for receiving an input signal; output terminal means for supplying an output signal having a logic value determined by said input signal; a first N channel transistor directly connected to said output terminal means and having source, drain and channel regions, said drain region including a high-impurity concentration region and a low-impurity concentration region located contiguous to said channel region, and said source region including a high-impurity concentration region contiguous to said channel region; a second N channel transistor connected between said first N channel transistor and a low potential, and having source, drain and channel regions, said drain and source regions each including high-impurity concentration regions located contiguous to said channel region; and first and second P channel transistors connected in parallel between said first N channel transistor and a high potential.

Claim 8

A logic circuit for an insulated gate type semiconductor device, comprising: input terminal means for receiving an input signal; output terminal means for supplying an output signal having a logic value determined by said input signal; a first N channel transistor directly connected to said output terminal means and having source, drain and channel regions, said drain region including a high-impurity concentration region and a low-impurity concentration region located contiguous to said channel region, and said source region including a high-impurity concentration region contiguous to said channel region; a second N channel transistor connected between said first N channel transistor and a low potential, and having source, drain and channel regions, said drain and source regions each including high-impurity concentration regions located contiguous to said channel region; and first and second P channel transistors connected in parallel between said first N channel transistor and a high potential.

Claim 9

A logic circuit for an insulated gate type semiconductor device according to claim 5 wherein said high-impurity concentration is higher than about 10 20 cm -3 , and said low-impurity concentration is lower than about 5×10 18 cm -3 .