US5255384A
Expired / Lapsed
US
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Memory address translation system having modifiable and non-modifiable translation mechanisms
Assignee: Intergraph Corp
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Filing: 1991-09-26
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Granted: 1993-10-19
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Expires: 2011-09-26
Abstract
Abstract A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the processor. The modifiable translation logic includes modifiable read-write memory, while the non-modifiable translation logic includes fixed combinational logic for providing predefined translations of predetermined virtual addresses to real addresses. A controller selectively accesses main memory on cache memory misses to load translation information and other data from main memory to the cache memory. In a preferred embodiment, the address translation logic provides an associated system tag defining access priorities and access modes with each address translation.
Inventors
- 👤 Howard G. Sachs
- 👤 James Y. Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/0862; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
236 words
In a computing system having a cache memory coupled to a processor via a processor/cache bus and to a main memory via a system bus, wherein the computing system operates in supervisor and user modes, a method of translating a virtual address to a real address comprising the steps of: receiving an externally supplied virtual address comprising a virtual segment address and a virtual page address; addressing a translation lookaside buffer with the virtual address for translating the virtual address to a real address; determining whether the virtual address was correctly translated by the translation lookaside buffer; addressing a dynamic address translation means with the virtual address for translating the virtual address to a real address if the virtual address was not correctly translated by the translation lookaside buffer; wherein the step of addressing the translation lookaside buffer comprises the steps of: addressing a plurality of read/write memory elements which translates virtual addresses to real addresses with bits from the virtual page address when the computing system operates in both the supervisor mode and the user mode; addressing hardwired combinational logic which translates predetermined virtual addresses to predefined real addresses with bits from the virtual segment address when the computing system is operating in the supervisor mode; and always preventing the dynamic address translation step whenever one of the predetermined virtual addresses is to be translated and the computing system is operating in the supervisor mode.
Claim 2
Dependent Claim
236 words
In a computing system having a cache memory coupled to a processor via a processor/cache bus and to a main memory via a system bus, wherein the computing system operates in supervisor and user modes, a method of translating a virtual address to a real address comprising the steps of: receiving an externally supplied virtual address comprising a virtual segment address and a virtual page address; addressing a translation lookaside buffer with the virtual address for translating the virtual address to a real address; determining whether the virtual address was correctly translated by the translation lookaside buffer; addressing a dynamic address translation means with the virtual address for translating the virtual address to a real address if the virtual address was not correctly translated by the translation lookaside buffer; wherein the step of addressing the translation lookaside buffer comprises the steps of: addressing a plurality of read/write memory elements which translates virtual addresses to real addresses with bits from the virtual page address when the computing system operates in both the supervisor mode and the user mode; addressing hardwired combinational logic which translates predetermined virtual addresses to predefined real addresses with bits from the virtual segment address when the computing system is operating in the supervisor mode; and always preventing the dynamic address translation step whenever one of the predetermined virtual addresses is to be translated and the computing system is operating in the supervisor mode.
Claim 3
Dependent Claim
196 words
In a computing system having a cache memory coupled to a processor via a processor/cache bus and to a main memory via a system bus, an address translation apparatus comprising: virtual address input means for receiving an externally supplied virtual address, the virtual address including a virtual segment address and a virtual page address; address translation means for selectively providing a real address output responsive to the virtual address, the address translation means comprising: modifiable translation means including modifiable read-write memory for translating virtual addresses to real addresses; and non-modifiable translation means for translating predetermined virtual addresses to predefined real addresses; translation addressing means, coupled to the virtual address input means and to the address translation means, for addressing the modifiable translation means with bits from the virtual page address and for simultaneously addressing the non-modifiable translation means with bits from the virtual segment address; predefined translation detecting means for detecting whether the virtual address is translatable by the non-modifiable translation means; and real address selecting means, responsive to the predefined translation detecting means, for selecting the real address from the non-modifiable translation means when the virtual address has been translated by the non-modifiable translation means.
Claim 4
Dependent Claim
196 words
In a computing system having a cache memory coupled to a processor via a processor/cache bus and to a main memory via a system bus, an address translation apparatus comprising: virtual address input means for receiving an externally supplied virtual address, the virtual address including a virtual segment address and a virtual page address; address translation means for selectively providing a real address output responsive to the virtual address, the address translation means comprising: modifiable translation means including modifiable read-write memory for translating virtual addresses to real addresses; and non-modifiable translation means for translating predetermined virtual addresses to predefined real addresses; translation addressing means, coupled to the virtual address input means and to the address translation means, for addressing the modifiable translation means with bits from the virtual page address and for simultaneously addressing the non-modifiable translation means with bits from the virtual segment address; predefined translation detecting means for detecting whether the virtual address is translatable by the non-modifiable translation means; and real address selecting means, responsive to the predefined translation detecting means, for selecting the real address from the non-modifiable translation means when the virtual address has been translated by the non-modifiable translation means.
Claim 5
Dependent Claim
30 words
The apparatus according to claim 2, wherein the translation addressing means addresses the non-modifiable translation means with bits from the virtual segment address and bits from the virtual page address.
Claim 6
Dependent Claim
24 words
The apparatus according to claim 3 wherein the translation addressing means addresses the modifiable translation means only with bits from the virtual page address.
Claim 7
Dependent Claim
54 words
The apparatus according to claim 2 wherein the virtual address comprises thirty-two bits designated [31 . . . 0], wherein the translation addressing means addresses the non-modifiable translation means with bits [31 . . . 15], and wherein the translation addressing means addresses the modifiable translation means with bits [17 . . . 12].
Claim 8
Dependent Claim
56 words
The apparatus according to claim 2 wherein the virtual address comprises thirty-two bits designated [31 . . . 0], wherein the translation addressing means addresses the non-modifiable translation means with only bits [31 . . . 15], and wherein the translation addressing means addresses the modifiable translation means with only bits [17 . . . 12].
Claim 9
Dependent Claim
15 words
The apparatus according to claim 2 wherein the non-modifiable translation means comprises hardwired combinational logic.
Claim 10
Dependent Claim
17 words
The apparatus according to claim 2 wherein the non-modifiable translation means comprises combinational logic and read-only memory.
Claim 11
Dependent Claim
88 words
The apparatus according to claim 2 wherein the computing system operates in supervisor and user modes and provides a mode signal indicating in which mode the computing system is operating, and wherein the non-modifiable translation means includes operation enabling means, responsive to the mode signal, for enabling the translation of the virtual address when the mode signal indicates the computing system is operating in supervisor mode and for disabling the translation of the virtual address when the mode signal indicates the computing system is operating in user method.
Claim 12
Dependent Claim
26 words
The apparatus according to claim 9 wherein the non-modifiable translation means translates the virtual address into a real address that is different from the virtual address.
Claim 13
Dependent Claim
29 words
The apparatus according to claim 9 wherein the non-modifiable translation means translates the virtual address into a real address corresponding to one of a plurality of selected address space.
Claim 14
Dependent Claim
50 words
The apparatus according to claim 9 wherein real addresses are provided for main memory space, input/output space, and boot ROM space, and wherein the non-modifiable translation means only translates the virtual address into a real address corresponding to one of the main memory space, input/output space, or boot ROM space.
Claim 15
Dependent Claim
49 words
The apparatus according to claim 9 wherein real addresses are provided for main memory space, input/output space, and boot ROM space, and wherein the non-modifiable translation means translates the virtual address into a real address corresponding to one of the main memory space, input/output space, or boot ROM space.
Claim 16
Dependent Claim
36 words
The apparatus according to claim 13 wherein real addresses are provided for addressing internal registers, and wherein the non-modifiable translation means translates the virtual address into a real address corresponding to one of the internal registers.
Claim 17
Dependent Claim
37 words
The apparatus according to claim 13 wherein real addresses for at least one of the main memory space, input/output space, or boot ROM space are different from the virtual address from which the real address was translated.
Claim 18
Dependent Claim
29 words
The apparatus according to claim 13 wherein real addresses for input/output space and boot ROM space are different from the virtual address from which the real address was translated.
Claim 19
Dependent Claim
42 words
The apparatus according to claim 13 wherein the non-modifiable translation means translates virtual addresses having virtual page addresses corresponding to pages 0, 1, 2, and 3 into a real address corresponding to pages 0, 1, 2, and 3 in main memory space.
Claim 20
Dependent Claim
37 words
The apparatus according to claim 13 wherein the non-modifiable translation means translates virtual addresses having virtual page addresses corresponding to pages 4 and 5 into a real address corresponding to pages 0 and 1 in input/output space.
Claim 21
Dependent Claim
38 words
The apparatus according to claim 13 wherein the non-modifiable translation means translates virtual address having virtual page addresses corresponding to pages 4 and 5 into a real address corresponding to pages 0 and 1 in boot ROM space.
Claim 22
Dependent Claim
116 words
The apparatus according to claim 9 wherein the modifiable translation means translates the virtual address when the computing system operates in both the supervisor mode and the user mode, and wherein the real address selecting means selects the real address derived from the non-modifiable translation means when the non-modifiable translation means is addressed by one of the predetermined virtual addresses when the computing system is operating in supervisor mode, and selects the real address derived from the modifiable translation means when: (i) the non-modifiable translation means is not addressed by one of the predetermined virtual addresses and the computing system is operating in supervisor mode; or (ii) the computing system is operating in the user mode.
Claim 23
Dependent Claim
51 words
The apparatus according to claim 20 wherein the modifiable read-write memory includes a plurality of lines of translation data, each line of translation data including the real address and a system tag, and wherein the real address corresponds to one of a plurality of address spaces designated by the system tag.
Claim 24
Dependent Claim
16 words
The apparatus according to claim 21 wherein each line of translation data includes protection level data.
References Cited (Backward Citations)
US3693165A
Cited
US3761881A
Cited
US3764996A
Cited
US3723976A
Cited
US3902164A
Cited
GB1444228A
Cited
US3898624A
Cited
US3956737A
Cited
US3896419A
Cited
US4057848A
Cited
US4037209A
Cited
US4068303A
Cited
US4173783A
Cited
US4077059A
Cited
US4151593A
Cited
US4144563A
Cited
US4181934A
Cited
US4229789A
Cited
US4161024A
Cited
US4276594A
Cited
US4189767A
Cited
US4500962A
Cited
US4215402A
Cited
US4208716A
Cited
US4253145A
Cited
US4433389A
Cited
US4295193A
Cited
US4315310A
Cited
US4354225A
Cited
US4405980A
Cited
US4502110A
Cited
US4392200A
Cited
US4360869A
Cited
US4398243A
Cited
US4493020A
Cited
US4381541A
Cited
US4386402A
Cited
US4481573A
Cited
US4407015A
Cited
US4482952A
Cited
US4439829A
Cited
US4400774A
Cited
US4407016A
Cited
US4513369A
Cited
US4507728A
Cited
US4445177A
Cited
US4456954A
Cited
US4464712A
Cited
US4563737A
Cited
US4498135A
Cited
US4604688A
Cited
US4654819A
Cited
US4581702A
Cited
US4635194A
Cited
JPS6041146A
Cited
US4682281A
Cited
JPS60120450A
Cited
US4680700A
Cited
JPS60144847A
Cited
US4669043A
Cited
US4680702A
Cited
US4620275A
Cited
US4685082A
Cited
US4899275A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-18 | 1997-04-19 | 1997-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-18 | 2001-04-19 | 2001-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-18 | 2005-04-19 | 2005-10-19 | $7700.00 | Window Closed / Lapsed |