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US5249101A
Expired / Lapsed
US
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Chip carrier with protective coating for circuitized surface
Assignee: International Business Machines Corp
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Filing: 1992-07-06
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Granted: 1993-09-28
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Expires: 2012-07-06
Abstract
Abstract A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.
Inventors
- 👤 Brenda D. Frey
- 👤 Charles A. Joseph
- 👤 Francis J. Olshefski
- 👤 James W. Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:01
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/121; H10W74/01; H10W74/012; H10W74/15; H10W74/40; H10W74/47; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/851; H10W72/853; H10W72/856; H10W72/874; H10W72/877; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/736; Y; Y10; Y10S; Y10S428/00; Y10S428/901
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
138 words
A chip carrier, comprising: a substrate including a surface bearing electrical circuitry; at least one semiconductor chip mounted on said surface via electrically conductive solder balls at least partially encapsulated in a first encapsulant having a composition which includes an epoxy, a coefficient of thermal expansion (CTE) of said first encapsulant being within 30 percent of a CTE of said solder balls; a second encapsulant which covers and thereby encapsulates at least a portion of said electrical circuitry on said substrate surface and which contacts and at least partially encircles at least a portion of said first encapsulant, Characterized In That said second encapsulant has a composition which includes a urethane and said composition is chosen so that said second encapsulant exhibits a modulus of elasticity equal to or less than about 10,000 psi at 25 degrees C.
Claim 2
Dependent Claim
138 words
A chip carrier, comprising: a substrate including a surface bearing electrical circuitry; at least one semiconductor chip mounted on said surface via electrically conductive solder balls at least partially encapsulated in a first encapsulant having a composition which includes an epoxy, a coefficient of thermal expansion (CTE) of said first encapsulant being within 30 percent of a CTE of said solder balls; a second encapsulant which covers and thereby encapsulates at least a portion of said electrical circuitry on said substrate surface and which contacts and at least partially encircles at least a portion of said first encapsulant, Characterized In That said second encapsulant has a composition which includes a urethane and said composition is chosen so that said second encapsulant exhibits a modulus of elasticity equal to or less than about 10,000 psi at 25 degrees C.
Claim 3
Dependent Claim
31 words
The chip carrier of claim 1, wherein said second encapsulant also covers and thereby encapsulates at least a portion of an upper, exposed surface of said at least one semiconductor chip.
Claim 4
Dependent Claim
25 words
The chip carrier of claim 1, further comprising a heat sink directly mounted on an upper, exposed surface of said at least one semiconductor chip.
Claim 5
Dependent Claim
174 words
A chip carrier, comprising: a substrate including a surface bearing electrical circuitry; at least one semiconductor chip mounted on said surface via electrically conductive solder balls at least partially encapsulated in a first encapsulant having a composition which includes an epoxy, a coefficient of thermal expansion (CTE) of said first encapsulant being within 30 percent of a CTE of said solder balls; a second encapsulant which covers and thereby encapsulates at least a portion of said electrical circuitry on said substrate surface and which contacts and at least partially encircles at least a portion of said first encapsulant, Characterized In That said second encapsulant has a composition which includes a urethane, said composition of said second encapsulant being chosen so that, when viewed under a 10× optical microscope, said second encapsulant exhibits neither internal cracks, nor cracks at an interface between said first and second encapsulants, when said chip carrier is subjected to thermal cycling between 0 degrees C. and 100 degrees C., at a frequency of three cycles per hour, for 2,000 cycles.
Claim 6
Dependent Claim
174 words
A chip carrier, comprising: a substrate including a surface bearing electrical circuitry; at least one semiconductor chip mounted on said surface via electrically conductive solder balls at least partially encapsulated in a first encapsulant having a composition which includes an epoxy, a coefficient of thermal expansion (CTE) of said first encapsulant being within 30 percent of a CTE of said solder balls; a second encapsulant which covers and thereby encapsulates at least a portion of said electrical circuitry on said substrate surface and which contacts and at least partially encircles at least a portion of said first encapsulant, Characterized In That said second encapsulant has a composition which includes a urethane, said composition of said second encapsulant being chosen so that, when viewed under a 10× optical microscope, said second encapsulant exhibits neither internal cracks, nor cracks at an interface between said first and second encapsulants, when said chip carrier is subjected to thermal cycling between 0 degrees C. and 100 degrees C., at a frequency of three cycles per hour, for 2,000 cycles.
Claim 7
Dependent Claim
165 words
A chip carrier comprising: a substrate including a surface bearing electrical circuitry; at least one semiconductor chip mounted on said surface via electrically conductive solder balls at least partially encapsulated in a first encapsulant having a composition which includes an epoxy, a coefficient of thermal expansion (CTE) of said first encapsulant being within 30 percent of a CTE of said solder balls; a second encapsulant which covers and thereby encapsulates at least a portion of said electrical circuitry on said substrate surface and which contacts and at least partially encircles at least a portion of said first encapsulant, Characterized In That said second encapsulant has a composition which includes a urethane, said composition of said second encapsulant being chosen so that, when viewed under a 10× optical microscope, said second encapsulant exhibits neither delamination from said substrate, nor cracking, when said chip carrier is thermally cycled from -40 degrees C. to +65 degrees C., at a frequency of one cycle per hour, for ten cycles.
Claim 8
Dependent Claim
165 words
A chip carrier comprising: a substrate including a surface bearing electrical circuitry; at least one semiconductor chip mounted on said surface via electrically conductive solder balls at least partially encapsulated in a first encapsulant having a composition which includes an epoxy, a coefficient of thermal expansion (CTE) of said first encapsulant being within 30 percent of a CTE of said solder balls; a second encapsulant which covers and thereby encapsulates at least a portion of said electrical circuitry on said substrate surface and which contacts and at least partially encircles at least a portion of said first encapsulant, Characterized In That said second encapsulant has a composition which includes a urethane, said composition of said second encapsulant being chosen so that, when viewed under a 10× optical microscope, said second encapsulant exhibits neither delamination from said substrate, nor cracking, when said chip carrier is thermally cycled from -40 degrees C. to +65 degrees C., at a frequency of one cycle per hour, for ten cycles.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-27 | 1997-03-29 | 1997-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-27 | 2001-03-29 | 2001-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-27 | 2005-03-29 | 2005-09-28 | $7700.00 | Window Closed / Lapsed |