Potential detecting circuit

Claim 2

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; a fourth terminal for receiving another potential; a first MOS transistor of a first conductivity type having a gate coupled to the fourth terminal, and a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal, wherein the first potential has an absolute valve greater than an absolute value of the second potential.

Claim 3

The potential detecting circuit according to claim 1, wherein said second potential is a positive potential, said first potential is another positive potential higher than said second potential, said first conductivity type is an N type, and said second conductivity type is a P type.

Claim 4

The potential detecting circuit according to claim 1, wherein said second potential is a negative potential, said first potential is another negative potential higher than said second potential, said first conductivity type is a P type, and said second conductivity type is an N type.

Claim 5

The potential detecting circuit according to claim 3, wherein a back-gate of said second MOS transistor is connected to the source of said first MOS transistor.

Claim 6

The potential detecting circuit according to claim 3, wherein said first MOS transistor is of the depletion type.

Claim 7

The potential detecting circuit according to claim 3, further including a level change circuit, responsive to a voltage at the drain of the second MOS transistor, for generating a converted potential having a value of said reference potential or of said second potential.

Claim 8

The potential detecting circuit according to claim 1, wherein a back-gate of said second MOS transistor is connected to the source of said first MOS transistor.

Claim 9

The potential detecting circuit according to claim 1, wherein said first MOS transistor is of the depletion type.

Claim 10

The potential detecting circuit according to claim 1, further including a level converting circuit, responsive to a voltage at the drain of the second MOS transistor, for generating a converted potential having a value of said reference potential or of said second potential.

Claim 11

The potential detecting circuit according to claim 1, wherein the first and second potentials are both positive, the first conductivity type is a P type, and the second conductivity type is an N type.

Claim 12

The potential detecting circuit according to claim 1, wherein the first MOS transistor is of the depletion type.

Claim 13

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; a fourth terminal for receiving another potential; a first MOS transistor of a first conductivity type having a gate coupled to the fourth terminal, a drain coupled to the first terminal, a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal means, and a gate coupled to the second terminal; and a detect voltage controller for producing said another potential depending on the input potential and applying said another potential to the fourth terminal, wherein the first potential has an absolute value greater than an absolute value of the second potential.

Claim 14

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; a fourth terminal for receiving another potential; a first MOS transistor of a first conductivity type having a gate coupled to the fourth terminal, a drain coupled to the first terminal, a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal means, and a gate coupled to the second terminal; and a detect voltage controller for producing said another potential depending on the input potential and applying said another potential to the fourth terminal, wherein the first potential has an absolute value greater than an absolute value of the second potential.

Claim 15

The potential detecting circuit according to claim 12, wherein said second potential is a positive potential, said first potential is another positive potential higher than said second potential, said first conductivity type is an N type, and said second conductivity type is a P type.

Claim 16

The potential detecting circuit according to claim 12, wherein said second potential is a negative potential, said first potential is another negative potential higher than said second potential, said first conductivity type is a P type, and said second conductivity type is an N type.

Claim 17

The potential detecting circuit according to claim 14, wherein a back-gate of said second MOS transistor is connected to the source of said first MOS transistor.

Claim 18

The potential detecting circuit according to claim 14, wherein said first MOS transistor is of the depletion type.

Claim 19

The potential detecting circuit according to claim 14, wherein said second MOS transistor does not contain a high breakdown voltage structure.

Claim 20

The potential detecting circuit according to claim 14, wherein when an absolute value of said input potential is higher than said second potential by a first amount, said detecting voltage controller produces an output potential determined by said input potential, and when the absolute value of said input potential is within a range whose upper limit is higher than the second potential by an amount less than the first amount and whose lower limit is lower than the second potential, said detect voltage controller produces said second potential.

Claim 21

The potential detecting circuit according to claim 18, wherein the first amount is approximately 15 volts.

Claim 22

The potential detecting circuit according to claim 14, wherein said detecting potential control block includes at least fourth and fifth MOS transistors of the first conductivity connected in series, a source and gate of said fifth MOS transistors being coupled to said second potential, a node between said fourth and fifth MOS transistors being coupled to the gate of said first MOS transistor, a gate and drain of said fourth MOS transistor being interconnected, and the gate and drain of said fourth MOS transistor being coupled to said input terminal.

Claim 23

The potential detecting circuit according to claim 14, further including a level converting circuit, responsive to a voltage at the drain of the second MOS transistor, for generating a converted potential having a value of said reference potential or of said second potential.

Claim 24

The potential detecting circuit according to claim 21, wherein the level converting circuit includes a fourth MOS transistor of the first conductivity type, having a drain coupled to the drain of the second MOS transistor, a gate coupled to the second potential, and a source; an inverter having an input coupled to the source of the fourth transistor.

Claim 25

The potential detecting circuit according to claim 12, wherein a back-gate of said second MOS transistor is connected to the source of said first MOS transistor.

Claim 26

The potential detecting circuit according to claim 12, wherein said first MOS transistor is of the depletion type.

Claim 27

The potential detecting circuit according to claim 12, wherein said second MOS transistor has a structure other than a high breakdown voltage structure.

Claim 28

The potential detecting circuit according to claim 12, wherein when an absolute value of said input potential is higher than said second potential by a first amount, said detect voltage controller produces an output potential determined by said input potential, and when the absolute value of said input potential is within a range whose upper limit is higher than the second potential by an amount less than the first amount and whose lower limit is lower than the second potential, said detect voltage controller produces said second potential.

Claim 29

The potential detecting circuit according to claim 26, wherein the first amount is approximately 15 volts.

Claim 30

The potential detecting circuit according to claim 12, wherein said detect voltage controller includes fourth and fifth MOS transistors of the first conductivity type connected in series, a source and gate of said fifth MOS transistor coupled to said second terminal, a node between said fourth and fifth MOS transistors coupled to the gate of said first MOS transistor, a gate and drain of said fourth MOS transistor being interconnected, and the gate and drain of said fourth MOS transistor being coupled to said input terminal.

Claim 31

The potential detecting circuit according to claim 12, further including a level converting circuit, responsive to a voltage at the drain of the second MOS transistor, for generating a converted potential having a value of said reference potential or of said second potential.

Claim 32

The potential detecting circuit according to claim 29, wherein the level converting circuit includes a fourth MOS transistor of the first conductivity type, having a drain coupled to the drain of the second MOS transistor, a gate coupled to the second potential, and a source; an inverter having an input coupled to the source of the fourth transistor.

Claim 33

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first positive potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; means for generating a potential depending on the input potential; first MOS transistor of a P type having a gate coupled to said means for generating a potential depending on the input potential, a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of an N type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, said second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the P type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal, wherein the first positive potential has an absolute value greater than an absolute value of the second potential.

Claim 34

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first positive potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; means for generating a potential depending on the input potential; first MOS transistor of a P type having a gate coupled to said means for generating a potential depending on the input potential, a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of an N type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, said second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the P type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal, wherein the first positive potential has an absolute value greater than an absolute value of the second potential.

Claim 35

A potential detecting circuit comprising: first means for receiving an input potential, the input potential having an absolute value equal to or lower than a first negative potential; second means for receiving a second potential; third means for receiving a reference voltage having an absolute value less than the absolute value of the second potential; means for generating a dependent potential varying in accordance with the input terminal; a first MOS transistor of a P type having a gate responsive to the dependent potential, and a drain coupled to the first means, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of an N type having a source coupled to the source of the first MOS transistor, a gate coupled to the second means, and a drain, said second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the P type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third means, and a gate coupled to the second potential; wherein the second potential is a negative potential, the first potential is another negative potential lower than the second potential, wherein the first negative potential has an absolute value greater than an absolute value of the second potential.

Claim 36

A potential detecting circuit comprising: first means for receiving an input potential, the input potential having an absolute value equal to or lower than a first negative potential; second means for receiving a second potential; third means for receiving a reference voltage having an absolute value less than the absolute value of the second potential; means for generating a dependent potential varying in accordance with the input terminal; a first MOS transistor of a P type having a gate responsive to the dependent potential, and a drain coupled to the first means, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of an N type having a source coupled to the source of the first MOS transistor, a gate coupled to the second means, and a drain, said second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the P type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third means, and a gate coupled to the second potential; wherein the second potential is a negative potential, the first potential is another negative potential lower than the second potential, wherein the first negative potential has an absolute value greater than an absolute value of the second potential.

Claim 37

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than the absolute value of the second potential; means for generating a dependent potential varying in accordance with the input potential; first MOS transistor of a first conductivity type and depletion type having gate responsive to the dependent potential, and a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, said second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal, wherein the first potential has an absolute valve greater than an absolute value of the second potential.

Claim 38

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than the absolute value of the second potential; means for generating a dependent potential varying in accordance with the input potential; first MOS transistor of a first conductivity type and depletion type having gate responsive to the dependent potential, and a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, said second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; and a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal, wherein the first potential has an absolute valve greater than an absolute value of the second potential.

Claim 39

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; means for generating a dependent potential varying in accordance with the input potential; a first MOS transistor of a first conductivity type having a gate responsive to the dependent potential, and a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal; and means, responsive to a potential on the drain of the second MOS transistor, for generating a signal having either the reference potential or the second potential, wherein the first potential has an absolute valve greater than an absolute value of the second potential.

Claim 40

A potential detecting circuit comprising: a first terminal for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; a second terminal for receiving a second potential; a third terminal for receiving a reference voltage having an absolute value less than an absolute value of the second potential; means for generating a dependent potential varying in accordance with the input potential; a first MOS transistor of a first conductivity type having a gate responsive to the dependent potential, and a drain coupled to the first terminal, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second terminal, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal, and a gate coupled to the second terminal; and means, responsive to a potential on the drain of the second MOS transistor, for generating a signal having either the reference potential or the second potential, wherein the first potential has an absolute valve greater than an absolute value of the second potential.

Claim 41

A potential detecting circuit comprising: first means for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; second means for receiving a second potential; third means for receiving a reference voltage having an absolute value less than an absolute value of the second potential; fourth means for receiving another potential; a first MOS transistor of a first conductivity type having a gate coupled to the fourth means, and a drain coupled to the first means, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second means, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal means, and a gate coupled to the second potential; and a level converting circuit, responsive to a voltage at the drain of the second MOS transistor, for generating a converted potential having a value of the reference potential or the second potential, including a fourth MOS transistor of the first conductivity type, having a drain coupled to the drain of the second MOS transistor, a gate coupled to the second means, and a source; and an inverter having an input coupled to the source of the fourth MOS transistor, wherein the first potential has an absolute value greater than an absolute value of the second potential.

Claim 42

A potential detecting circuit comprising: first means for receiving an input potential, the input potential having an absolute value equal to or lower than a first potential; second means for receiving a second potential; third means for receiving a reference voltage having an absolute value less than an absolute value of the second potential; fourth means for receiving another potential; a first MOS transistor of a first conductivity type having a gate coupled to the fourth means, and a drain coupled to the first means, and a source, the first MOS transistor being characterized by a certain breakdown voltage; a second MOS transistor of a second conductivity type having a source coupled to the source of the first MOS transistor, a gate coupled to the second means, and a drain, the second MOS transistor being characterized by a breakdown voltage substantially lower than the certain breakdown voltage; a third MOS transistor of the first conductivity type having a drain coupled to the drain of the second MOS transistor, a source coupled to the third terminal means, and a gate coupled to the second potential; and a level converting circuit, responsive to a voltage at the drain of the second MOS transistor, for generating a converted potential having a value of the reference potential or the second potential, including a fourth MOS transistor of the first conductivity type, having a drain coupled to the drain of the second MOS transistor, a gate coupled to the second means, and a source; and an inverter having an input coupled to the source of the fourth MOS transistor, wherein the first potential has an absolute value greater than an absolute value of the second potential.