US4658156A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage detection circuit for detecting input voltage larger in absolute value than power supply voltage
Assignee: NEC Electronics Corp
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Filing: 1984-12-07
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Granted: 1987-04-14
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Expires: 2004-12-07
Abstract
Abstract A voltage detection circuit for detecting an input voltage larger in absolute value than a power supply voltage is disclosed. This circuit comprises a first transistor connected between a terminal supplied with the input voltage and a circuit node, and a second and a third complementary transistors connected in series between the circuit node and a reference potential terminal. The first transistor is used as a voltage-dropping means, and the gates of the second and third transistors are commonly supplied with the power supply voltage. When the potential difference between the circuit node and the gate of the second transistor exceeds the threshold value of the same transistor, the second transistor is turned ON and the potential at the connection point of the second and third transistors begins to change. At this time, the input voltage is higher in absolute value than the power supply voltage because the first transistor operates as the voltage-dropping means.
Inventors
- 👤 Kiyokazu Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:50
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/30; H03K17/302; G; G01; G01R; G01R19/00; G01R19/165; G01R19/16504; G01R19/16519; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C5/00; G11C5/14; G11C5/143
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A detection circuit for detecting an application of an input voltage which is higher in absolute value than a power voltage, comprising: an input terminal supplied with said input voltage; a power terminal supplied with said power voltage; a reference terminal supplied with a reference potential; a first field effect transistor having drain-source current path connected between said input terminal and said first node and a gate short-circuited with a drain, said first field effect transistor operating as a diode to supply said first node with a voltage that is lower in absolute value than said input voltage by a threshold voltage of said first field effect transistor; a second field effect transistor having a drain-source current path connected between said first node and said second node and a gate connected directly to said power terminal; a third field effect transistor having a source-drain current path connected between said second node and said reference terminal and a gate connected directly to said power terminal, said second and third field effect transistors being different in conductivity type from each other; and an inverter operative with said power voltage and said reference potential and having its input terminal connected to said second node, said inverter producing a detection output signal indicating that said input voltage has a level higher in absolute value than a sum voltage of said power voltage, said threshold voltage of said first field effect transistor and a threshold voltage of said second field effect transistor.
Claim 2
Dependent Claim
247 words
A detection circuit for detecting an application of an input voltage which is higher in absolute value than a power voltage, comprising: an input terminal supplied with said input voltage; a power terminal supplied with said power voltage; a reference terminal supplied with a reference potential; a first field effect transistor having drain-source current path connected between said input terminal and said first node and a gate short-circuited with a drain, said first field effect transistor operating as a diode to supply said first node with a voltage that is lower in absolute value than said input voltage by a threshold voltage of said first field effect transistor; a second field effect transistor having a drain-source current path connected between said first node and said second node and a gate connected directly to said power terminal; a third field effect transistor having a source-drain current path connected between said second node and said reference terminal and a gate connected directly to said power terminal, said second and third field effect transistors being different in conductivity type from each other; and an inverter operative with said power voltage and said reference potential and having its input terminal connected to said second node, said inverter producing a detection output signal indicating that said input voltage has a level higher in absolute value than a sum voltage of said power voltage, said threshold voltage of said first field effect transistor and a threshold voltage of said second field effect transistor.
Claim 3
Dependent Claim
42 words
The circuit as claimed in claim 1, wherein said first field effect transistor is the same conductivity type as said third field effect transistor, the gate and drain of said first field effect transistor being connected in common to said input terminal.
Claim 4
Dependent Claim
234 words
A programmable read only memory device comprising: a programming terminal supplied with a programming voltage; a power terminal supplied with a power voltage; a reference terminal supplied with a reference potential; a plurality of memory cells; means responsive to address signals for selecting at least one of said memory cells; a detection circuit for detecting an application of said programming voltage higher in absolute value than said power voltage and producing a detection signal; and means responsive to said detection signal for supplying said programming voltage to the selected memory cell; said detection circuit including a first node and a second node; a first field effect transistor connected between said programming terminal and said first node and having a gate of said first field effect transistor connected to a drain of said first field effect transistor; a second field effect transistor of a first channel type connected between said first node and said second node and having a gate of said second field effect transistor connected directly to said power supply; a third field effect transistor of a second channel type connected between said second node and said reference terminal and having a gate of said third field effect transistor connected directly to said power supply; and an inverter operative with said power voltage and said reference potential and having its input terminal connected to said second node, said inverter producing said detection signal.
Claim 5
Dependent Claim
234 words
A programmable read only memory device comprising: a programming terminal supplied with a programming voltage; a power terminal supplied with a power voltage; a reference terminal supplied with a reference potential; a plurality of memory cells; means responsive to address signals for selecting at least one of said memory cells; a detection circuit for detecting an application of said programming voltage higher in absolute value than said power voltage and producing a detection signal; and means responsive to said detection signal for supplying said programming voltage to the selected memory cell; said detection circuit including a first node and a second node; a first field effect transistor connected between said programming terminal and said first node and having a gate of said first field effect transistor connected to a drain of said first field effect transistor; a second field effect transistor of a first channel type connected between said first node and said second node and having a gate of said second field effect transistor connected directly to said power supply; a third field effect transistor of a second channel type connected between said second node and said reference terminal and having a gate of said third field effect transistor connected directly to said power supply; and an inverter operative with said power voltage and said reference potential and having its input terminal connected to said second node, said inverter producing said detection signal.
Claim 6
Dependent Claim
226 words
An integrated circuit comprising: a power terminal supplied with a power voltage; a reference terminal supplied with a reference potential; a signal terminal; a transistor circuit supplied through said signal terminal with an input signal, said input signal taking a level that is within a range between said power voltage and said reference potential upon a steady operation mode, said signal terminal being supplied with a testing voltage upon a test operation mode, said testing voltage taking a level that is higher in absolute value than said power voltage; a detection circuit detecting an application of said testing voltage to said signal terminal; and a test circuit testing said transistor circuit in response to said detection signal; said detection circuit including a first field effect transistor connected between said signal terminal and a first node and having a gate of said first field effect transistor connected to a drain of said first field effect transistor; a second field effect transistor of a first conductivity type connected between said first node and a second node and having a gate of said second field effect transistor connected directly to said power terminal; and a third field effect transistor of a second conductivity type connected between said second node and said reference terminal and having a gate of said third field effect transistor connected directly to said power terminal.
Claim 7
Dependent Claim
226 words
An integrated circuit comprising: a power terminal supplied with a power voltage; a reference terminal supplied with a reference potential; a signal terminal; a transistor circuit supplied through said signal terminal with an input signal, said input signal taking a level that is within a range between said power voltage and said reference potential upon a steady operation mode, said signal terminal being supplied with a testing voltage upon a test operation mode, said testing voltage taking a level that is higher in absolute value than said power voltage; a detection circuit detecting an application of said testing voltage to said signal terminal; and a test circuit testing said transistor circuit in response to said detection signal; said detection circuit including a first field effect transistor connected between said signal terminal and a first node and having a gate of said first field effect transistor connected to a drain of said first field effect transistor; a second field effect transistor of a first conductivity type connected between said first node and a second node and having a gate of said second field effect transistor connected directly to said power terminal; and a third field effect transistor of a second conductivity type connected between said second node and said reference terminal and having a gate of said third field effect transistor connected directly to said power terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-13 | 1990-10-13 | 1991-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-13 | 1994-10-13 | 1995-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-13 | 1998-10-13 | 1999-04-14 | $7700.00 | Window Closed / Lapsed |