US4587447A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input signal level converter for an MOS digital circuit
Assignee: Siemens AG
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Filing: 1984-05-04
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Granted: 1986-05-06
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Expires: 2004-05-04
Abstract
Abstract An input signal level converter for applying a TTL signal to an actual input of an MOS circuit is required for n-MOS digital circuits controlled with TTL signals. This circuit forms a Schmitt trigger and comprises five MOS field effect transistors and a bootstrap capacitor. The transistors are preferably of the n-channel type and are self-inhibiting. This circuit is improved by means of two further transistors connected such that a quiescent current consumption of the level converter is considerably reduced. Favorable dynamic behavior is achieved without having unfavorable current usage.
Inventors
- 👤 Manfred Baehring
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K19/0175; H03K19/0185; H03K19/018507; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
262 words
An input signal level converter for combination with an MOS digital circuit comprising: a signal input for connection to a TTL signal and connected for control of first and second MOS field effect transistors; a source terminal of the first transistor being connected to reference potential and its drain terminal connecting to a source terminal of the second transistor and also through a source-drain path of a third MOS field effect transistor to a supply potential; a drain terminal of the second transistor connecting to a signal output of the converter, and connecting to the supply potential via a parallel connection of a fourth MOS field effect transistor and a series connection of a bootstrap capacitor and a fifth MOS field effect transistor connected as a resistor; the signal output being directly connected to a signal input of said MOS digital circuit, said MOS digital circuit having a same reference potential and a same supply potential as the signal level converter; sixth and seventh MOS field effect transistors; a source terminal of the sixth transistor connecting to a drain terminal of the first transistor and its gate being connected to a gate of the first transistor; a drain terminal of the sixth transistor being connected to a gate of the third transistor, a drain terminal of the seventh transistor, and a gate of the fourth transistor; and a source terminal of the seventh transistor connecting to said bootstrap capacitor, and also connecting to a source terminal of the fifth transistor, and a gate of the seventh transistor connecting to its source terminal.
Claim 2
Dependent Claim
262 words
An input signal level converter for combination with an MOS digital circuit comprising: a signal input for connection to a TTL signal and connected for control of first and second MOS field effect transistors; a source terminal of the first transistor being connected to reference potential and its drain terminal connecting to a source terminal of the second transistor and also through a source-drain path of a third MOS field effect transistor to a supply potential; a drain terminal of the second transistor connecting to a signal output of the converter, and connecting to the supply potential via a parallel connection of a fourth MOS field effect transistor and a series connection of a bootstrap capacitor and a fifth MOS field effect transistor connected as a resistor; the signal output being directly connected to a signal input of said MOS digital circuit, said MOS digital circuit having a same reference potential and a same supply potential as the signal level converter; sixth and seventh MOS field effect transistors; a source terminal of the sixth transistor connecting to a drain terminal of the first transistor and its gate being connected to a gate of the first transistor; a drain terminal of the sixth transistor being connected to a gate of the third transistor, a drain terminal of the seventh transistor, and a gate of the fourth transistor; and a source terminal of the seventh transistor connecting to said bootstrap capacitor, and also connecting to a source terminal of the fifth transistor, and a gate of the seventh transistor connecting to its source terminal.
Claim 3
Dependent Claim
12 words
The converter claim 1 wherein the converter is constructed of N-channel MOSFETs.
Claim 4
Dependent Claim
14 words
The level converter according to claim 1 wherein said level converter is monolithically integrated.
Claim 5
Dependent Claim
210 words
An input signal level converter for use with an MOS digital circuit, comprising: a signal input connected to gates of first and second MOS field effect transistors; the first and second transistors being connected in series and a third MOS field effect transistor having a source-drain path connected between a supply potential and a junction between the first and second transistors; the source-drain paths of the first, second, and a fourth MOS field effect transistor being connected in series between the supply potential and a reference potential; an output connected at a junction between the second and fourth transistors; a gate of the third transistor connecting between the second and fourth transistors; a bootstrap capacitor connected in series with a fifth MOS field effect transistor between the output and the supply potential; a gate of the fourth transistor connecting between the capacitor and fifth transistor and a gate of the fifth transistor connecting to the supply potential; a series connection of sixth and seventh MOS field effect transistors connecting between the bootstrap capacitor and a junction between the first and second transistors; a gate of the sixth transistor connecting to the gate of the first and second transistors; and a gate of the seventh transistor connecting to the bootstrap capacitor.
Claim 6
Dependent Claim
210 words
An input signal level converter for use with an MOS digital circuit, comprising: a signal input connected to gates of first and second MOS field effect transistors; the first and second transistors being connected in series and a third MOS field effect transistor having a source-drain path connected between a supply potential and a junction between the first and second transistors; the source-drain paths of the first, second, and a fourth MOS field effect transistor being connected in series between the supply potential and a reference potential; an output connected at a junction between the second and fourth transistors; a gate of the third transistor connecting between the second and fourth transistors; a bootstrap capacitor connected in series with a fifth MOS field effect transistor between the output and the supply potential; a gate of the fourth transistor connecting between the capacitor and fifth transistor and a gate of the fifth transistor connecting to the supply potential; a series connection of sixth and seventh MOS field effect transistors connecting between the bootstrap capacitor and a junction between the first and second transistors; a gate of the sixth transistor connecting to the gate of the first and second transistors; and a gate of the seventh transistor connecting to the bootstrap capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |