US4540898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clocked buffer circuit using a self-bootstrapping transistor
Assignee: Motorola Solutions Inc
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Filing: 1983-03-07
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Granted: 1985-09-10
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Expires: 2003-03-07
Abstract
Abstract A clocked buffer circuit is provided which uses a self-bootstrapping transistor to provide a full power supply output signal in response to an input signal and a full power supply clock signal. The self-bootstrapping transistor is disabled by a delay circuit prior to the removal of the clock signal so that the output signal is still provided after the removal of the clock signal. That the output signal reaches full power supply is ensured because the disabling effect of the delay circuit is triggered by the output signal itself.
Inventors
- 👤 Joseph Pumo
- 👤 Marc J. E. Belleville
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
121 words
A clocked buffer circuit for providing an output signal in response to an input signal and a clock signal, comprising: a NOR gate having an output, a first input for receiving an inverted input signal, and a second input; a first transistor having a control electrode coupled to the output of the NOR gate, a first current electrode for receiving the clock signal, and a second current electrode for providing the output signal; and delay means having an input for receiving the output signal and an output coupled to the second input of the NOR gate for providing a delay signal responsive to the output signal, wherein the delay signal is delayed in time from the occurrence of the output signal.
Claim 2
Dependent Claim
121 words
A clocked buffer circuit for providing an output signal in response to an input signal and a clock signal, comprising: a NOR gate having an output, a first input for receiving an inverted input signal, and a second input; a first transistor having a control electrode coupled to the output of the NOR gate, a first current electrode for receiving the clock signal, and a second current electrode for providing the output signal; and delay means having an input for receiving the output signal and an output coupled to the second input of the NOR gate for providing a delay signal responsive to the output signal, wherein the delay signal is delayed in time from the occurrence of the output signal.
Claim 3
Dependent Claim
22 words
The clocked buffer circuit of claim 1 further comprising means for removing the output signal in response to a second clock signal.
Claim 4
Dependent Claim
148 words
A clocked buffer circuit for providing an output signal in response to an input signal and a clock signal, comprising: a first transistor having a control electrode for receiving the input signal, a first current electrode for receiving a clock signal, and a second current electrode for providing the output signal; a second transistor having a control electrode coupled to the second current electrode of the first transistor for receiving the output signal, a first current electrode coupled to a first power supply terminal, and a second current electrode; resistive means for providing resistance between the second current electrode of the second transistor and a second power supply terminal; and a third transistor having a control electrode coupled to the second current electrode of the second transistor, a first current electrode coupled to ground, and a second current electrode coupled to the control electrode of the first transistor.
Claim 5
Dependent Claim
148 words
A clocked buffer circuit for providing an output signal in response to an input signal and a clock signal, comprising: a first transistor having a control electrode for receiving the input signal, a first current electrode for receiving a clock signal, and a second current electrode for providing the output signal; a second transistor having a control electrode coupled to the second current electrode of the first transistor for receiving the output signal, a first current electrode coupled to a first power supply terminal, and a second current electrode; resistive means for providing resistance between the second current electrode of the second transistor and a second power supply terminal; and a third transistor having a control electrode coupled to the second current electrode of the second transistor, a first current electrode coupled to ground, and a second current electrode coupled to the control electrode of the first transistor.
Claim 6
Dependent Claim
47 words
The clocked buffer circuit of claim 3 further comprising a fourth transistor having a control electrode for receiving an inverted input signal, a first current electrode coupled to the second power supply terminal, and a second current electrode coupled to the control electrode of the first transistor.
Claim 7
Dependent Claim
72 words
The clocked buffer circuit of claim 4 comprising a fifth transistor interposed between the second current electrode of the fourth transistor and the control electrode of the first transistor, wherein said fifth transistor has a control electrode coupled to the first power supply terminal, a first current electrode coupled to the second current electrode of the fourth transistor, and a second current electrode coupled to the control electrode of the first transistor.
Claim 8
Dependent Claim
28 words
The clocked buffer circuit of claim 5 further comprising second resistive means coupled between the first power supply terminal and the second current electrode of the fourth transistor.
Claim 9
Dependent Claim
48 words
The clocked buffer circuit of claim 6 further comprising a sixth transistor having a control electrode for receiving a second clock signal, a first current electrode coupled to the second power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor.
Claim 10
Dependent Claim
47 words
The clocked buffer circuit of claim 2 further comprising a fourth transistor having a control electrode for receiving a second clock signal, a first current electrode coupled to a power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-09 | 1989-03-11 | 1989-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-09 | 1993-03-11 | 1993-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-09 | 1997-03-11 | 1997-09-10 | $7700.00 | Window Closed / Lapsed |