US3774055A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clocked bootstrap inverter circuit
Assignee: National Semiconductor Corp
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Filing: 1972-01-24
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Granted: 1973-11-20
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Expires: 1992-01-24
Abstract
Abstract A clocked bootstrap inverter circuit including an inverting amplifier, an active load for the inverting amplifier including a capacitive bootstrapping circuit, a biasing circuit responsive to a first clocking signal and a second clocking signal 180* out of phase with the first clocking signal, and an amplifier disabling device responsive to a third clocking signal which is more than 180* out of phase with the first clocking signal. The biasing circuit alternately activates and inactivates the active load while the disabling device alternately disables the amplifier and provides a small time delay for allowing the bootstrapping circuit to be precharged.
Inventors
- 👤 D Bapat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
300 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal, said amplifier including a first FET having a first gate for receiving said input signal, a first source coupled to said first source of potential and a first drain coupled to said output terminal; an active load means for said amplifier including a bootstrapping circuit, said load means having a conductive state and a nonconductive state, said load means including a second FET having a second gate, a second source coupled to aid output terminal and a second drain coupled to said second source of potential; biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a third FET and a fourth FET, said third FET having a third gate for receiving said first clocking signal, a third source coupled to said second gate, and a third drain coupled to said second source of potential, said fourth FET having a fourth gate for receiving a second clocking signal which is 180* out of phase with said first clocking signal, a fourth source coupled to said first source of potential and a fourth drain coupled to said second gate; and disabling means responsive to a third clocking signal and operative to periodically disable said amplifier, said disabling means including a fifth FET having a fifth gate for receiving said third clocking signal, a fifth source coupled to said first source of potential, and a fifth drain coupled to said output terminal, said third clocking signal being more than 180* out of phase with said first clocking signal.
Claim 2
Dependent Claim
300 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal, said amplifier including a first FET having a first gate for receiving said input signal, a first source coupled to said first source of potential and a first drain coupled to said output terminal; an active load means for said amplifier including a bootstrapping circuit, said load means having a conductive state and a nonconductive state, said load means including a second FET having a second gate, a second source coupled to aid output terminal and a second drain coupled to said second source of potential; biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a third FET and a fourth FET, said third FET having a third gate for receiving said first clocking signal, a third source coupled to said second gate, and a third drain coupled to said second source of potential, said fourth FET having a fourth gate for receiving a second clocking signal which is 180* out of phase with said first clocking signal, a fourth source coupled to said first source of potential and a fourth drain coupled to said second gate; and disabling means responsive to a third clocking signal and operative to periodically disable said amplifier, said disabling means including a fifth FET having a fifth gate for receiving said third clocking signal, a fifth source coupled to said first source of potential, and a fifth drain coupled to said output terminal, said third clocking signal being more than 180* out of phase with said first clocking signal.
Claim 3
Dependent Claim
198 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal, said amplifier including a first FET having a first gate for receiving said input signal, a first source coupled to said first source of potential and a first drain coupled to said outut terminal; an active load means for said amplifier including a boot-strapping circuit, said load means having a conductive state and a nonconductive state, said load means including a second FET having a second gate, a second source coupled to said output terminal and a second drain coupled to said second source of potential; biasing means responsive to said first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a third FET having a third gate coupled to said second source of potential, a third source coupled to said second gate, and a third drain for receiving said first clocking signal; and disabling means responsive to a second clocking signal and operative to periodically disable said amplifier.
Claim 4
Dependent Claim
198 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal, said amplifier including a first FET having a first gate for receiving said input signal, a first source coupled to said first source of potential and a first drain coupled to said outut terminal; an active load means for said amplifier including a boot-strapping circuit, said load means having a conductive state and a nonconductive state, said load means including a second FET having a second gate, a second source coupled to said output terminal and a second drain coupled to said second source of potential; biasing means responsive to said first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a third FET having a third gate coupled to said second source of potential, a third source coupled to said second gate, and a third drain for receiving said first clocking signal; and disabling means responsive to a second clocking signal and operative to periodically disable said amplifier.
Claim 5
Dependent Claim
63 words
A clocked bootstrap inverter circuit as recited in claim 2 wherein said disabling means includes a fourth FET having a fourth gate for receiving said second clocking signal, a fourth source coupled to said first source of potential, and a fourth drain coupled to said output terminal, said second clocking signal being more than 180* out of phase with said first clocking signal.
Claim 6
Dependent Claim
233 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal; an active load means for said amplifier including a boot-strapping circuit, said load means having a conductive state and a nonconductive state; said load means including a first FET having a first gate, a first source coupled to said output terminal, and a second drain coupled to said second source of potential; biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including, a second FET responsive to said first clocking signal and operative to couple said first gate to said second source of potential, and a third FET responsive to a second clocking signal and operative to couple said first gate to said first source of potential, said second clocking signal being 180* out of phase with said first clocking signal; and disabling means responsive to a third clocking signal and operative to periodically disable said amplifier, said disabling means including a fourth FET responsive to said third clocking signal and operative to couple said output terminal to said first source of potential, said third clocking signal being more than 180* out of phase with said first clocking signal.
Claim 7
Dependent Claim
233 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal; an active load means for said amplifier including a boot-strapping circuit, said load means having a conductive state and a nonconductive state; said load means including a first FET having a first gate, a first source coupled to said output terminal, and a second drain coupled to said second source of potential; biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including, a second FET responsive to said first clocking signal and operative to couple said first gate to said second source of potential, and a third FET responsive to a second clocking signal and operative to couple said first gate to said first source of potential, said second clocking signal being 180* out of phase with said first clocking signal; and disabling means responsive to a third clocking signal and operative to periodically disable said amplifier, said disabling means including a fourth FET responsive to said third clocking signal and operative to couple said output terminal to said first source of potential, said third clocking signal being more than 180* out of phase with said first clocking signal.
Claim 8
Dependent Claim
189 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal; an active load means for said amplifier including a bootstrapping circuit, said load means having a conductive state and a nonconductive state, said load means including a first FET having a first gate, a first source coupled to said output terminal, and a first drain coupled to said second source of potential; biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a second FET having a second gate coupled to said second source of potential, a second source coupled to said first gate, and a third drain for receiving said first clocking signal; disabling means responsive to a second clocking signal and operative to periodically disable said amplifier, said disabling means including a third FET responsive to said second clocking signal and operative to couple said output terminal to said first source of potential.
Claim 9
Dependent Claim
189 words
A clocked bootstrap inverter circuit comprising a first source of potential; a second source of potential; an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal; an active load means for said amplifier including a bootstrapping circuit, said load means having a conductive state and a nonconductive state, said load means including a first FET having a first gate, a first source coupled to said output terminal, and a first drain coupled to said second source of potential; biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a second FET having a second gate coupled to said second source of potential, a second source coupled to said first gate, and a third drain for receiving said first clocking signal; disabling means responsive to a second clocking signal and operative to periodically disable said amplifier, said disabling means including a third FET responsive to said second clocking signal and operative to couple said output terminal to said first source of potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-19 | 1977-05-21 | 1977-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-19 | 1981-05-21 | 1981-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-19 | 1985-05-21 | 1985-11-20 | $7700.00 | Window Closed / Lapsed |