US3660684A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage level output driver circuit
Assignee: Boeing North American Inc
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Filing: 1971-02-17
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Granted: 1972-05-02
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Expires: 1991-02-17
Abstract
Abstract The output is precharged to a voltage level slightly in excess of the threshold voltage level of the field effect transistors implementing the driver circuit. A bootstrap circuit is used for decreasing the time required to drive the output to the voltage level. A feedback circuit from the output disables the bootstrap circuit for limiting the output voltage level and for reducing additional power consumption in the circuit after the output has been driven to the required voltage level. An input evaluation circuit changes the output voltage level or permits it to remain unchanged as a function of the input voltage level.
Inventors
- 👤 Clarence W Padgett
- 👤 Robert W Polkinghorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
214 words
A low level output driver circuit having an operation cycle determined by multiple phase clock signals, said cycle having an output precharge interval and an input evaluation interval occurring during each cycle oF said multiple phase clock signals, said driver circuit comprising, a load field effect transistor connected between the output and a voltage source, an output precharge circuit for charging the output to a relatively low voltage level during an output precharge operating interval of the driver, an input evaluation circuit for evaluating inputs to said low level output driver circuit during an evaluation interval of the operation of the driver. said precharge circuit including a first field effect transistor connected between the gate electrode of said load field effect transistor and a second voltage level and having its gate electrode connected to the output for disabling said output precharge circuit after the output has been charged to said relatively low voltage level during the output precharge operating interval, Said precharge circuit further including a first bootstrap field effect transistor driver connected between the gate electrode of said load field effect transistor and a voltage source for providing a drive voltage to said gate electrode during said output precharge operating interval before said precharge circuit is disabled by said first field effect transistor.
Claim 2
Dependent Claim
214 words
A low level output driver circuit having an operation cycle determined by multiple phase clock signals, said cycle having an output precharge interval and an input evaluation interval occurring during each cycle oF said multiple phase clock signals, said driver circuit comprising, a load field effect transistor connected between the output and a voltage source, an output precharge circuit for charging the output to a relatively low voltage level during an output precharge operating interval of the driver, an input evaluation circuit for evaluating inputs to said low level output driver circuit during an evaluation interval of the operation of the driver. said precharge circuit including a first field effect transistor connected between the gate electrode of said load field effect transistor and a second voltage level and having its gate electrode connected to the output for disabling said output precharge circuit after the output has been charged to said relatively low voltage level during the output precharge operating interval, Said precharge circuit further including a first bootstrap field effect transistor driver connected between the gate electrode of said load field effect transistor and a voltage source for providing a drive voltage to said gate electrode during said output precharge operating interval before said precharge circuit is disabled by said first field effect transistor.
Claim 3
Dependent Claim
195 words
The driver circuit recited in claim 1 wherein said output precharge circuit further includes second and third field effect transistors connected in electrical series between the gate electrode of said field effect transistor bootstrap driver and a second voltage level for operating in conjunction with said first field effect transistor for disabling said precharge circuit during the output precharge operation interval after said output has been charged to said relatively low voltage level, said second field effect transistor having its gate electrode connected to the output and third field effect transistor having its gate electrode connected to a multiple phase clock signal for rendering said third field effect transistor conductive during the output precharge interval and non-conductive during other intervals of the operating cycle, and a fourth field effect transistor connected between a voltage source and the gate electrode of the first bootstrap field effect transistor driver for providing a voltage to the gate electrode during a phase prior to the output precharge interval, said third phase effect transistor being nonconductive during said preceding phase for enabling said voltage level to be applied to the gate electrode of said first bootstrap field effect transistor driver.
Claim 4
Dependent Claim
111 words
The driver circuit recited in claim 2 further including a fifth field effect transistor connected between the output and a second voltage level, a second bootstrap field effect transistor driver for driving the gate electrode of said fifth field effect transistor, said driver including capacitance, a sixth field effect transistor for precharging the capacitance of the second bootstrap field effect transistor driver during the input evaluation interval, and means responsive to the input voltage level during the input evaluation interval for controlling the output of said second bootstrap field effect transistor driver whereby the fifth field effect transistor is rendered conductive or nonconductive as a function of the input voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-02 | 1975-11-01 | 1976-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-02 | 1979-11-01 | 1980-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-02 | 1983-11-01 | 1984-05-02 | $7700.00 | Window Closed / Lapsed |