Protocol for transfer of DMA data

Claim 2

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a memory controller, a first system resource bus coupled to a system resource, and a data router, wherein the data router includes switching logic for coupling the memory controller to the first system resource bus, and wherein the process comprises the following steps: transmitting DMA setup information designating a setup write transaction, from the memory controller to the system resource to indicate an upcoming DMA transfer, via the data router and via the first system resource bus coupled to said system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said system resource to said memory controller or a down direction from said memory controller to said system resource, and indicates whether said DMA transfer will involve said first system resource bus; decoding said DMA setup information in the data router, to determine the direction of said DMA transfer, and to determine whether said DMA transfer will involve said first system resource bus; transmitting a start DMA code, from said memory controller to said system resource, via the data router and via said first system resource bus coupled to said system resource; configuring the switching logic in said data router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said switching logic is configured to forward DMA data, from said first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve said first system resource bus; and wherein said switching logic is configured to forward DMA data, from said memory controller to said first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve said first system resource bus; transmitting an acknowledge code, from said system resource to said memory controller, via said first system resource bus coupled to said system resource, and via the switching logic in said data router, in response to transmission of said start DMA code; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said system resource to said memory controller, via said first system resource bus coupled to said system resource, and via the switching logic in said data router; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from said memory controller to said system resource, via the switching logic in said data router, and via said first system resource bus coupled to said system resource; and transmitting a done code, after transmission of DMA data, from said system resource to said memory controller, via said first system resource bus coupled to said system resource, and via the switching logic in said data router, to indicate successful DMA data transmission.

Claim 3

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a memory controller, a first system resource bus coupled to a first system resource, a second system resource bus coupled to a second system resource, and a data router, wherein the data router includes switching logic for coupling the memory controller to the first system resource bus or to the second system resource bus, and wherein the process comprises the following steps: transmitting DMA setup information designating a setup write transaction, from the memory controller to one of the system resources to indicate an upcoming DMA transfer, via the data router and via the system resource bus coupled to said one system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said one system resource to said memory controller or a down direction from said memory controller to said one system resource, and indicates which system resource bus the DMA transfer will involve; decoding said DMA setup information in the data router, to determine the direction of said DMA transfer, and to determine which system resource bus said DMA transfer will involve; transmitting a start DMA code, from said memory controller to said one system resource, via the data router and via the system resource bus coupled to said one system resource; configuring the switching logic in said date router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said switching logic is configured to forward DMA data, from the first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said switching logic is configured to forward DMA data, from the second system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said switching logic is configured to forward DMA data, from said memory controller to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said switching logic is configured to forward DMA data, from said memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus; transmitting an acknowledge code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, in response to transmission of said start DMA code; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from said memory controller to said one system resource, via the switching logic in said data router, and via the system resource bus coupled to said one system resource; and transmitting a done code, after transmission of DMA data, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, to indicate successful DMA data transmission.

Claim 4

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a memory controller, a first system resource bus coupled to a first system resource, a second system resource bus coupled to a second system resource, and a data router, wherein the data router includes switching logic for coupling the memory controller to the first system resource bus or to the second system resource bus, and wherein the process comprises the following steps: transmitting DMA setup information designating a setup write transaction, from the memory controller to one of the system resources to indicate an upcoming DMA transfer, via the data router and via the system resource bus coupled to said one system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said one system resource to said memory controller or a down direction from said memory controller to said one system resource, and indicates which system resource bus the DMA transfer will involve; decoding said DMA setup information in the data router, to determine the direction of said DMA transfer, and to determine which system resource bus said DMA transfer will involve; transmitting a start DMA code, from said memory controller to said one system resource, via the data router and via the system resource bus coupled to said one system resource; configuring the switching logic in said date router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said switching logic is configured to forward DMA data, from the first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said switching logic is configured to forward DMA data, from the second system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said switching logic is configured to forward DMA data, from said memory controller to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said switching logic is configured to forward DMA data, from said memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus; transmitting an acknowledge code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, in response to transmission of said start DMA code; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from said memory controller to said one system resource, via the switching logic in said data router, and via the system resource bus coupled to said one system resource; and transmitting a done code, after transmission of DMA data, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, to indicate successful DMA data transmission.

Claim 5

A process in accordance with claim 2, and further comprising: transmitting an error code, from the switching logic in said data router, to said memory controller, after transmission of said acknowledge code, to indicate unsuccessful DMA data transmission.

Claim 6

A process in accordance with claim 3, and further comprising: transmitting a stall code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, after transmission of said acknowledge code, to indicate said one system resource is not ready to accept DMA data transmitted in the down direction from said memory controller at times when the DMA transfer is in the down direction and to indicate said one system resource is not ready to send DMA data in the up direction at times when the DMA transfer is in the up direction.

Claim 7

A process in accordance with claim 2, and further comprising: transmitting an error code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, after transmission of DMA data in the up direction, to indicate an error in DMA data transmission.

Claim 8

A process in accordance with claim 5, and further comprising: transmitting a stall code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, after transmission of said acknowledge code, to indicate said one system resource is not ready to send DMA data in the up direction.

Claim 9

A process in accordance with claim 5, in which the error code is a CRC error code to indicate a CRC error in DMA data transmission.

Claim 10

A process in accordance with claim 7, and further comprising: transmitting a stall code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, after transmission of said acknowledge code, to indicate said one system resource is not ready to send DMA data in the up direction.

Claim 11

A process in accordance with claim 2, and further comprising: transmitting a stall code, from said one system resource to said memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in said data router, after transmission of said acknowledge code, to indicate said one system resource is not ready to accept DMA data transmitted in the down direction from said memory controller at times when the DMA transfer is in the down direction and to indicate said one system resource is not ready to send DMA data in the up direction at times when the DMA transfer is in the up direction.

Claim 12

A process in accordance with claims 2, 3, 4, 5, 6, or 9, wherein said switching logic includes downstream and upstream switching logic, and wherein the process comprises: configuring the downstream and upstream switching logic in said data router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said upstream switching logic is configured to forward codes, from the first system resource bus to said memory controller, at times when said DMA transfer will involve the first system resource bus; wherein said upstream switching logic is configured to forward codes, from the second system resource bus to said memory controller, at times when said DMA transfer will involve the second system resource bus; wherein said upstream switching logic is configured to forward DMA data, from the first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said upstream switching logic is configured to forward DMA data, from the second system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said downstream switching logic is configured to forward DMA data, from said memory controller to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said downstream switching logic is configured to forward DMA data, from said memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus.

Claim 13

A process in accordance with claim 2, 3, 4, 5, 6, or 9, wherein said one system resource has a count register for indicating the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer, and further comprising: transmitting DMA count information during a write transaction, from the memory controller to said one system resource, via the data router and via the system resource bus coupled to said one system resource, prior to transmission of said start DMA code from said memory controller to said one system resource, wherein said DMA count information specifies a DMA count of the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer; storing the DMA count in the count register in said one system resource, after transmission of said DMA count information from said memory controller to said one system resource.

Claim 14

A process in accordance with claim 11, wherein said switching logic includes downstream and upstream switching logic, and wherein the process comprises: configuring the downstream and upstream switching logic in said data router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said upstream switching logic is configured to forward codes, from the first system resource bus to said memory controller, at times when said DMA transfer will involve the first system resource bus; wherein said upstream switching logic is configured to forward codes, from the second system resource bus to said memory controller, at times when said DMA transfer will involve the second system resource bus; wherein said upstream switching logic is configured to forward DMA data, from the first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said upstream switching logic is configured to forward DMA data, from the second system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said downstream switching logic is configured to forward DMA data, from said memory controller to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said downstream switching logic is configured to forward DMA data, from said memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus.

Claim 15

A process in accordance with claims 2, 3, 4, 5, 6, or 9, wherein said one system resource has a pointer register for indicating a DMA data address to be accessed by said one system resource, and further comprising: transmitting DMA starting address information during a write transaction, from the memory controller to said one system resource, via the data router and via the system resource bus coupled to said one system resource, prior to transmission of said start DMA code from said memory controller to said one system resource, wherein said DMA starting address information specifies a DMA data address to be accessed by said one system resource during said DMA transfer; storing the DMA data address in the pointer register in said one system resource, after transmission of said DMA starting address information from said memory controller to said one system resource.

Claim 16

A process in accordance with claim 13, wherein said one system resource has a count register for indicating the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer, and further comprising: transmitting DMA count information during a write transaction, from the memory controller to said one system resource, via the data router and via the system resource bus coupled to said one system resource, prior to transmission of said start DMA code from said memory controller to said one system resource, wherein said DMA count information specifies a DMA count of the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer; storing the DMA count in the count register in said one system resource, after transmission of said DMA count information from said memory controller to said one system resource.

Claim 17

A process in accordance with claim 13, wherein said switching logic includes downstream and upstream switching logic, and wherein the process comprises: configuring the downstream and upstream switching logic in said data router, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by said data router; wherein said upstream switching logic is configured to forward codes, from the first system resource bus to said memory controller, at times when said DMA transfer will involve the first system resource bus; wherein said upstream switching logic is configured to forward codes, from the second system resource bus to said memory controller, at times when said DMA transfer will involve the second system resource bus; wherein said upstream switching logic is configured to forward DMA data, from the first system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said upstream switching logic is configured to forward DMA data, from the second system resource bus to said memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said downstream switching logic is configured to forward DMA data, from said memory controller to the first syterm resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first stystem resource bus; and wherein said downstream switching logic is configured to forward DMA data, from said memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus.

Claim 18

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a first memory controller, a second memory controller, a first system resource bus coupled to a first syterm resource, a second system resource bus coupled to a second system resource, a first data router coupled to the first memory controller, to the first system resource bus, and to the second system resource bus, and a second data router coupled to the second memory controller, to the first system resource bus, and to the second system resource bus, wherein each of the data routers includes switching logic, and wherein the process comprises the following steps: transmitting DMA setup information designating a setup write transaction, from one of the memory controller to one of the system resources to indicate an upcoming DMA transfer, via the data router coupled to said one memory controller and via the system resource bus coupled to said one system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said one system resource to said one memory controller or a down direction from said one memory controller to said one system resource, and indicates which system resource bus the DMA transfer will involve; decoding said DMA setup information in the data router coupled to said one memory controller, to determine the direction of said DMA transfer, and to determine which system resource bus said DMA transfer will involve; transmitting a start DMA code, from said one memory controller to said one system resource, via the data router coupled to said one memory controller and via the system resource bus coupled to said one system resource; configuring the switching logic in the data router coupled to said one memory controller, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the data router coupled to said one memory controller; wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from the first system resource bus to said one memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from the second system resource bus to said one memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from said one memory controller to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from said one memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus; transmitting an acknowledge code, from said one system resource to said one memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in the data router coupled to said one memory controller, in response to transmission of said start DMA code; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said one system resource to said one memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in the data router coupled to said one memory controller; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from said one memory controller to said one system resource, via the switching logic in the data router coupled to said one memory controller, and via the system resource bus coupled to said one system resource; and transmitting a done code, after transmission of DMA data, from said one system resource to said one memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in the data router coupled to said one memory controller, to indicate successful DMA data transmission.

Claim 19

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a first memory controller, a second memory controller, a first system resource bus coupled to a first syterm resource, a second system resource bus coupled to a second system resource, a first data router coupled to the first memory controller, to the first system resource bus, and to the second system resource bus, and a second data router coupled to the second memory controller, to the first system resource bus, and to the second system resource bus, wherein each of the data routers includes switching logic, and wherein the process comprises the following steps: transmitting DMA setup information designating a setup write transaction, from one of the memory controller to one of the system resources to indicate an upcoming DMA transfer, via the data router coupled to said one memory controller and via the system resource bus coupled to said one system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said one system resource to said one memory controller or a down direction from said one memory controller to said one system resource, and indicates which system resource bus the DMA transfer will involve; decoding said DMA setup information in the data router coupled to said one memory controller, to determine the direction of said DMA transfer, and to determine which system resource bus said DMA transfer will involve; transmitting a start DMA code, from said one memory controller to said one system resource, via the data router coupled to said one memory controller and via the system resource bus coupled to said one system resource; configuring the switching logic in the data router coupled to said one memory controller, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the data router coupled to said one memory controller; wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from the first system resource bus to said one memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from the second system resource bus to said one memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from said one memory controller to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said switching logic in the data router coupled to said one memory controller is configured to forward DMA data, from said one memory controller to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus; transmitting an acknowledge code, from said one system resource to said one memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in the data router coupled to said one memory controller, in response to transmission of said start DMA code; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said one system resource to said one memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in the data router coupled to said one memory controller; transmitting DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from said one memory controller to said one system resource, via the switching logic in the data router coupled to said one memory controller, and via the system resource bus coupled to said one system resource; and transmitting a done code, after transmission of DMA data, from said one system resource to said one memory controller, via the system resource bus coupled to said one system resource, and via the switching logic in the data router coupled to said one memory controller, to indicate successful DMA data transmission.

Claim 20

A process in accordance with claim 16, wherein the first data router is coupled to the second system resource bus via the switching logic in the second data router, and the second data router is coupled to the first system resource bus via the switching logic in the first data router, and wherein the process comprises the following steps: transmitting the same DMA setup information, from each of the memory controllers to one of the system resources to indicate the upcoming DMA transfer, via the first and second data routers and via the system resource bus coupled to said one system resource; decoding said DMA setup information in the first and second data routers; transmitting the start DMA code, from each of said memory controllers to said one system resource, via the first and second data routers and via the system resource bus coupled to said one system resource; configuring the switching logic in the first and second data routers in accordance with said DMA setup information decoded by the first and second data routers; wherein said switching logic in the first and second data routers is configured to forward DMA data, from the first system resource bus, via the switching logic in the first data router to the first memory controller, and via the switching logic in the first and second data routers to the second memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said switching logic in the first and second data routers is configured to forward DMA data, from the second system resource bus, via the switching logic in the second data router to the second memory controller, and via the switching logic in the second and first data routers to the first memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said switching logic in the first and second data routers is configured to forward DMA data, from the first memory controller via the switching logic in the first data router, and from the second memory controller via the switching logic in the second and first data routers, to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said switching logic in the first and second data routers is configured to forward DMA data, from the first memory controller via the switching logic in the first and second data routers, and from the second memory controller via the switching logic in the second data router, to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus; transmitting the acknowledge code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers; transmitting the same DMA data, at times when said DMA transfer is in the up direction, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers; transmitting the same DMA data, at times when said DMA transfer is in the down direction, from each of said memory controller to said one system resource, via the switching logic in the first and second data routers, and via the system resource bus coupled to said one system resource; transmitting a done code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers.

Claim 21

A process in accordance with claim 17 and further comprising: transmitting an error code, from the switching logic in the first and second data routers, to each of said memory controllers, after transmission of said acknowledge code, to indicate unsuccessful DMA data transmission.

Claim 22

A process in accordance with claim 18, and further comprising: transmitting a stall code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers, after transmission of said acknowledge code, to indicate said one system resource is not ready to accept DMA data transmitted in the down direction from each of said memory controllers at times when the DMA transfer is in the down direction and to indicate said one system resource is not ready to send DMA data in the up direction at times when the DMA transfer is in the up direction.

Claim 23

A process in accordance with claim 17, and further comprising: transmitting an error code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers, after transmission of DMA data in the up direction, to indicate an error in DMA data transmission.

Claim 24

A process in accordance with claim 20, and further comprising: transmitting a stall code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers, after transmission of said acknowledge code, to indicate said one system resource is not ready to send DMA data in the up direction.

Claim 25

A process in accordance with claim 20, in which the error code is a CRC error code to indicate a CRC error in DMA data transmission.

Claim 26

A process in accordance with claim 22, and further comprising: transmitting a stall code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers, after transmission of said acknowledge code, to indicate said one system resource is not ready to send DMA data in the up direction.

Claim 27

A process in accordance with claim 17, and further comprising: transmitting a stall code, from said one system resource to each of said memory controllers, via the system resource bus coupled to said one system resource, and via the switching logic in the first and second data routers, after transmission of said acknowledge code, to indicate said one system resource is not ready to accept DMA data transmitted in the down direction from each of said memory controllers at times when the DMA transfer is in the down direction and to indicate said one system resource is not ready to send DMA data in the up direction at times when the DMA transfer is in the up direction.

Claim 28

A process in accordance with claims 17, 18, 19, 20, 21, or 24, wherein said switching logic in the first and second data routers includes downstream and upstream switching logic, and wherein the process comprises: configuring the downstream and upstream switching logic in the first and second data routers, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the first and second data routers; wherein said upstream switching logic in the first and second data routers is configured to forward codes, from the first system resource bus, via the first data router to said first memory controller, and via the first and second data routers to said second memory controller, at times when said DMA transfer will involve the first system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward codes, from the second system resource bus, via the second data router to said second memory controller, and via the second and first data routers to said first memory controller, at times when said DMA transfer will involve the second system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward DMA data, from the first system resource bus, via the first data router to said first memory controller, and via the first and second data routers to said second memory controller, a times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward DMA data, from the second system resource bus, via the second data router to said second memory controller, and via the second and first data routers to said first memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said downstream switching logic in the first and second data routers is configured to forward DMA data, from said first memory controller via the first data router, and from said second memory controller via the second and first data routers, to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said downstream switching logic in the first and second data routers is configured to forward DMA data, from said second memory controller via the second data router, and from said first memory controller via the first and second data routers, to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus.

Claim 29

A process in accordance with claims 17, 18, 19, 20, 21, or 24, wherein said one system resource has a count register for indicating the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer, and further comprising: transmitting DMA count information during a write transaction, from each of said memory controllers to said one system resource, via the first and second data routers and via the system resource bus coupled to said one system resource, prior to transmission of said start DMA code from each of said memory controllers to said one system resource, wherein said DMA count information specifies a DMA count of the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer; storing the DMA count in the count register in said one system resource, after transmission of said DMA count information from each of said memory controllers to said one system resource.

Claim 30

A process in accordance with claim 26, wherein said switching logic in the first and second data routers includes downstream and upstream switching logic, and wherein the process comprises: configuring the downstream and upstream switching logic in the first and second data routers, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the first and second data routers; wherein said upstream switching logic in the first and second data routers is configured to forward codes, from the first system resource bus, via the first data router to said first memory controller, and via the first and second data routers to said second memory controller, at times when said DMA transfer will involve the first system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward codes, from the second system resource bus, via the second data router to said second memory controller, and via the second and first data routers to said first memory controller, at times when said DMA transfer will involve the second system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward DMA data, from the first system resource bus, via the first data router to said first memory controller, and via the first and second data routers to said second memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward DMA data, from the second system resource bus, via the second data router to said second memory controller, and via the second and first data routers to said first memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said downstream switching logic in the first and second data routers is configured to forward DMA data, from said first memory controller via the first data router, and from said second memory controller via the second and first data routers, to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said downstream switching logic in the first and second data routers is configured to forward DMA data, from said second memory controller via the second data router, and from said first memory controller via the first and second data routers, to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus.

Claim 31

A process in accordance with claims 17, 18, 19, 20, 21, or 24, wherein said one system resource has a pointer register for indicating a DMA data address to be accessed by said one system resource, and further comprising: transmitting DMA starting address information during a write transaction, from each of said memory controllers to said one system resource, via the first and second data routers and via the system resource bus coupled to said one system resource, prior to transmission of said start DMA code from each of said memory controllers to said one system resource, wherein said DMA starting address information specifies a DMA data address to be accessed by said one system resource during said DMA transfer; storing the DMA data address in the pointer register in said one system resource, after transmission of said DMA starting address information from each of said memory controllers to said one system resource.

Claim 32

A process in accordance with claim 28, wherein said one system resource has a count register for indicating the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer, and further comprising: transmitting DMA count information during a write transaction, from each of said memory controllers to said one system resource, via the first and second data routers and via the system resource bus coupled to said one system resource, prior to transmission of said start DMA code from each of said memory controllers to said one system resource, wherein said DMA count information specifies a DMA count of the number of bytes of DMA data to be accessed by said one system resource during said DMA transfer; storing the DMA count in the count register in said one system resource, after transmission of said DMA count information from each of said memory controllers to said one system resource.

Claim 33

A process in accordance with claim 28, wherein said switching logic in the first and second data routers includes downstream and upstream switching logic, and wherein the process comprises: configuring the downstream and upstream switching logic in the first and second data routers, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the first and second data routers; wherein said upstream switching logic in the first and second data routers is configured to forward codes, from the first system resource bus, via the first data router to said first memory controller, and via the first and second data routers to said second memory controller, at times when said DMA transfer will involve the first system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward codes, from the second system resource bus, via the second data router to said second memory controller, and via the second and first data routers to said first memory controller, at times when said DMA transfer will involve the second system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward DMA data, from the first system resource bus, via the first data router to said first memory controller, and via the first and second data routers to said second memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the first system resource bus; wherein said upstream switching logic in the first and second data routers is configured to forward DMA data, from the second system resource bus, via the second data router to said second memory controller, and via the second and first data routers to said first memory controller, at times when said DMA transfer is in the up direction and said DMA transfer will involve the second system resource bus; wherein said downstream switching logic in the first and second data routers is configured to forward DMA data, from said first memory controller via the first data router, and from said second memory controller via the second and first data routers, to the first system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the first system resource bus; and wherein said downstream switching logic in the first and second data routers is configured to forward DMA data, from said second memory controller via the second data router, and from said first memory controller via the first and second data routers, to the second system resource bus, at times when said DMA transfer is in the down direction and said DMA transfer will involve the second system resource bus.

Claim 34

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a first primary memory controller, a first mirror memory controller, a second primary memory controller, a second mirror memory controller, a first primary system resource bus and a first mirror system resource bus coupled to a first system resource, a second primary system resource bus and a first mirror system resource bus coupled to a second system resource, a first primary data router coupled to the first primary memory controller and to the first primary system resource bus, a first mirror data router coupled to the first mirror memory controller and to the first mirror system resource bus, a second primary data router coupled to the second primary memory controller and to the second primary system resource bus, a second mirror data router coupled to the second mirror memory controller and to the second mirror system resource bus, wherein each of the data routers includes switching logic for coupling the memory controllers to the system resource buses, wherein the first data routers are coupled to the second system resource buses via the switching logic in the second data routers, and the second data routers are coupled to the first system resource buses via the switching logic in the first data routers, and wherein the process comprises the following steps: transmitting the same DMA setup information designating a setup write transaction, from each of the memory controllers to one of the system resources to indicate an upcoming DMA transfer, via the first and second data routers and via the pair of system resource buses coupled to said one system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said one system resource to said memory controllers or a down direction from said memory controllers to said one system resource, and indicates which pair of system resource buses the DMA transfer will involve; decoding said DMA setup information in the first and second data routers, to determine the direction of said DMA transfer, and to determine which pair of system resource buses said DMA transfer will involve; transmitting a start DMA code, from each of said memory controllers to said one system resource, via the first and second data routers, and via the pair of system resource buses coupled to said one system resource; configuring the switching logic in the first and second data routers, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the first and second data routers; wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from the pair of first system resource buses, via the switching logic in the pair of first data routers to the pair of first memory controllers, and via the switching logic in the pairs of first and second data routers to the pair of second memory controllers, at times when said DMA transfer is in the up direction and said DMA transfer will involve the pair of first system resource buses; wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from the pair of second system resource buses, via the switching logic in the pair of second data routers to the pair of second memory controllers, and via the switching logic in the pairs of second and first data routers to the pair of first memory controllers, at times when said DMA transfer is in the up direction and said DMA transfer will involve the pair of second system resource buses; wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from one of the first memory controllers via the switching logic in one of the first data routers, and from one of the second memory controllers via the switching logic in one of the second data routers and the other first data router, to the pair of first system resource buses, at times when said DMA transfer is in the down direction and said DMA transfer will involve the pair of first system resource buses; and wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from one of the first memory controllers via the switching logic in one of the first data routers and one of the second data routers, and from one of the second memory controllers via the switching logic in the other second data router, to the pair of second system resource buses, at times when said DMA transfer is in the down direction and said DMA transfer will involve the pair of second system resource buses; transmitting an acknowledge code, from said one system resource to each of said memory controllers, via the pair of system resource buses coupled to said one system resource, and via the switching logic in the first and second data routers, in response to transmission of said start DMA code; transmitting the same DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said one system resource to each of said memory controllers, via the pair of system resource buses coupled to said one system resource, and via the switching logic in the first and second data routers; transmitting the same DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from one of the first memory controllers and from one of the second memory controllers to said one system resource, via the switching logic in the first and second data routers, and via the pair of system resource buses coupled to said one system resource; and transmitting a done code, after transmission of DMA data, from said one system resource to each of said memory controllers, via the pair of system resource buses coupled to said one system resource, and via the switching logic in the first and second data routers, to indicate successful DMA data transmission.

Claim 35

A process for transferring data via DMA between components in a computer system, wherein the computer system includes a first primary memory controller, a first mirror memory controller, a second primary memory controller, a second mirror memory controller, a first primary system resource bus and a first mirror system resource bus coupled to a first system resource, a second primary system resource bus and a first mirror system resource bus coupled to a second system resource, a first primary data router coupled to the first primary memory controller and to the first primary system resource bus, a first mirror data router coupled to the first mirror memory controller and to the first mirror system resource bus, a second primary data router coupled to the second primary memory controller and to the second primary system resource bus, a second mirror data router coupled to the second mirror memory controller and to the second mirror system resource bus, wherein each of the data routers includes switching logic for coupling the memory controllers to the system resource buses, wherein the first data routers are coupled to the second system resource buses via the switching logic in the second data routers, and the second data routers are coupled to the first system resource buses via the switching logic in the first data routers, and wherein the process comprises the following steps: transmitting the same DMA setup information designating a setup write transaction, from each of the memory controllers to one of the system resources to indicate an upcoming DMA transfer, via the first and second data routers and via the pair of system resource buses coupled to said one system resource, wherein said DMA setup information corresponds to said upcoming DMA transfer, and indicates a direction of the DMA transfer as either an up direction from said one system resource to said memory controllers or a down direction from said memory controllers to said one system resource, and indicates which pair of system resource buses the DMA transfer will involve; decoding said DMA setup information in the first and second data routers, to determine the direction of said DMA transfer, and to determine which pair of system resource buses said DMA transfer will involve; transmitting a start DMA code, from each of said memory controllers to said one system resource, via the first and second data routers, and via the pair of system resource buses coupled to said one system resource; configuring the switching logic in the first and second data routers, in response to transmission of said start DMA code, and in accordance with said DMA setup information decoded by the first and second data routers; wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from the pair of first system resource buses, via the switching logic in the pair of first data routers to the pair of first memory controllers, and via the switching logic in the pairs of first and second data routers to the pair of second memory controllers, at times when said DMA transfer is in the up direction and said DMA transfer will involve the pair of first system resource buses; wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from the pair of second system resource buses, via the switching logic in the pair of second data routers to the pair of second memory controllers, and via the switching logic in the pairs of second and first data routers to the pair of first memory controllers, at times when said DMA transfer is in the up direction and said DMA transfer will involve the pair of second system resource buses; wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from one of the first memory controllers via the switching logic in one of the first data routers, and from one of the second memory controllers via the switching logic in one of the second data routers and the other first data router, to the pair of first system resource buses, at times when said DMA transfer is in the down direction and said DMA transfer will involve the pair of first system resource buses; and wherein said switching logic in the pairs of first and second data routers is configured to forward DMA data, from one of the first memory controllers via the switching logic in one of the first data routers and one of the second data routers, and from one of the second memory controllers via the switching logic in the other second data router, to the pair of second system resource buses, at times when said DMA transfer is in the down direction and said DMA transfer will involve the pair of second system resource buses; transmitting an acknowledge code, from said one system resource to each of said memory controllers, via the pair of system resource buses coupled to said one system resource, and via the switching logic in the first and second data routers, in response to transmission of said start DMA code; transmitting the same DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the up direction, from said one system resource to each of said memory controllers, via the pair of system resource buses coupled to said one system resource, and via the switching logic in the first and second data routers; transmitting the same DMA data, after transmission of said acknowledge code, at times when said DMA transfer is in the down direction, from one of the first memory controllers and from one of the second memory controllers to said one system resource, via the switching logic in the first and second data routers, and via the pair of system resource buses coupled to said one system resource; and transmitting a done code, after transmission of DMA data, from said one system resource to each of said memory controllers, via the pair of system resource buses coupled to said one system resource, and via the switching logic in the first and second data routers, to indicate successful DMA data transmission.