Method and arrangement for transfer of data information to two parallelly working computer means

Claim 2

In a system which includes two parallelly operating data processor means, said data processing means including means for executing accordant instruction sequences in corresponding time intervals which may be mutually time displaced wherein each of the instruction sequences includes one input transfer instruction which can be activated in response to an interrupt signal, the method of transferring a number of units of data information to the data processor means in response to an external demand for a data transfer to the data processor means from an external source, the demand occurring asynchronously with respect to the execution of the instruction sequences, said data transfer method comprising the steps of continuously accumulating the number of time intervals each of the data processor means is passing through in the execution of the instruction sequences, registering the unit of data information to be transferred in response to the receipt of one of the external demands, registering a count value equal to the accumulated numbers if the data processor means are processing in corresponding time intervals,

Claim 3

registering a count value equal to the accumulated number associated with the data processor means which has executed the greater number of time intervals, if the data processing means are not processing in corresponding time intervals transferring an interrupt signal to each data processor means whenever the count of the number of time intervals executed by a data processor means has a predetermined relation with respect to said registered count value after the occurrence of a demand, and presenting the registered unit of data information to both of the data processor means.

Claim 4

registering a count value equal to the accumulated number associated with the data processor means which has executed the greater number of time intervals, if the data processing means are not processing in corresponding time intervals transferring an interrupt signal to each data processor means whenever the count of the number of time intervals executed by a data processor means has a predetermined relation with respect to said registered count value after the occurrence of a demand, and presenting the registered unit of data information to both of the data processor means.

Claim 5

The method of claim 1 wherein said predetermined relationship is equality.

Claim 6

The method of claim 1 wherein one is added to the registered count value between the registering of the count value step and the start of the transferring step.

Claim 7

The method of claim 1 further comprising the steps of buffer storing a subsequent unit of data information until the registered unit of data information has been transferred to both data processor means.

Claim 8

In a system which includes two parallelly operating data processor means, said data processing means including means for executing accordant instruction sequences in corresponding time intervals which may be mutually time displaced wherein each of the instruction sequences includes one input transfer instruction which can be activated in response to an interrupt signal, apparatus for transferring units of data information to the data processor means in response to an external demand for a data transfer to the data processor means from an external source, the demand occurring asynchronously with respect to the execution of the instruction sequences, said apparatus comprising: first and second counting means for counting the number of time intervals passed through by one and the other of the data processor means, respectively; an information registration means, connected to both data processing means, for registering one of the units of data information prior to transfer to said data processor means; a marking signal generating means for generating a marking signal in response to the receipt of an external demand for a data transfer to the data processor means; a number registration means for registering transfer values and having an input and an output; a reversing switch means having inputs connected to each of said counting means and an output, and including means for disconnecting from said output the input thereof connected to the counting means with the lower count; first and second comparator means, each of said comparator means having first and second inputs and an output for emitting an interrupt signal whenever the numbers received at said first and second inputs are equal, the output of said first comparator means being connected to one of the data processor means and a first input thereof being connected to said first counting means, the output of said second comparator means being connected to the other of the data processor means and a first input thereof being connected to said second counting means, and the second input of both of said comparator means being connected to a common terminal; and control means responsive to said marking signal generating means for alternatively connecting the output of said reversing switch means to the input of said number registration means or the output of said number registration means to said common terminal in accordance with the absence or presence of a marking signal.

Claim 9

In a system which includes two parallelly operating data processor means, said data processing means including means for executing accordant instruction sequences in corresponding time intervals which may be mutually time displaced wherein each of the instruction sequences includes one input transfer instruction which can be activated in response to an interrupt signal, apparatus for transferring units of data information to the data processor means in response to an external demand for a data transfer to the data processor means from an external source, the demand occurring asynchronously with respect to the execution of the instruction sequences, said apparatus comprising: first and second counting means for counting the number of time intervals passed through by one and the other of the data processor means, respectively; an information registration means, connected to both data processing means, for registering one of the units of data information prior to transfer to said data processor means; a marking signal generating means for generating a marking signal in response to the receipt of an external demand for a data transfer to the data processor means; a number registration means for registering transfer values and having an input and an output; a reversing switch means having inputs connected to each of said counting means and an output, and including means for disconnecting from said output the input thereof connected to the counting means with the lower count; first and second comparator means, each of said comparator means having first and second inputs and an output for emitting an interrupt signal whenever the numbers received at said first and second inputs are equal, the output of said first comparator means being connected to one of the data processor means and a first input thereof being connected to said first counting means, the output of said second comparator means being connected to the other of the data processor means and a first input thereof being connected to said second counting means, and the second input of both of said comparator means being connected to a common terminal; and control means responsive to said marking signal generating means for alternatively connecting the output of said reversing switch means to the input of said number registration means or the output of said number registration means to said common terminal in accordance with the absence or presence of a marking signal.

Claim 10

The apparatus of claim 5 wherein said information registration means comprises an information register having an input and an output connected to both said data processor means for transmitting units of data information thereof, an information buffer means for storing units of data information for sequential presentation to the input of said information register, and a first gating means responsive to said marking signal generating means for controlling the passage of units of data information from said information buffer means to said information register; and wherein said marking signal generating means comprises a reaction gating means for controlling the operation of said first gating means and having an output connected thereto, a first input adapted to receive a signal associated with the external demand, first and second bistable flip-flop means, each having first state inputs connected to the output of said reaction gating means and second state inputs respectively connected to the one and the other data processor means, and respective outputs, a marking gating means having inputs connected to the outputs of said flip-flop means and an output connected to the second input of said reaction gating means and said first gating means.

Claim 11

The apparatus of claim 5 wherein said number registration means further comprises a unit adder for incrementing by-one values received from said counting means before transfer to said comparator means.