Program timing circuitry for central data processor of digital communications system

Claim 1

A recovery program timer system for a data processing system having a central data processor including processing circuits and maintenance circuits, an interrupt control circuit for generating an interrupt control circuit sequence level signal to start an interrupt cycle, and a recovery control circuit for generating an enable recovery program timing level signal when a recovery program is called, said timer responsive to said enable recovery program timing level signal to initiate a recovery program cycle, said timer comprising: recovery program register means for accumulating and storing signals representative of a count of machine cycles of said central processor; incrementing circuit means for incrementing the stored count signals in said recovery program register means each cycle time of said sentral processor, including overflow signal producing means, said interrupt control circuit sequence level signal initializing the incrementing circuit means to zero count; recovery program timer bistable circuit means responsive to said enable recovery program timing level signal for actuating said recovery program register means; and logic circuit means responsive to a recovery program punch-in signal and said overflow signal from said incrementing circuitry for generating a recovery program timing error level signal only if said punch-in signal and said overflow signal do not occur at the same time when said recovery program timer is operating in a normal mode.