Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
272 words
Apparatus for providing a remote multiplexer terminal with a failover capability from a first central processor unit to a second central processor unit without loss of data, said remote multiplexer terminal being a data acquisition and control system capable of receiving data at a clocked rate from a multiplicity of input/output devices and after processing that data according to a software program, delivering the results to an external equipment, the software program additionally serving to designate the first central processor unit as the "Master" and the second central processor unit as the "Slave", the apparatus being integral with the central processor units and comprising: dual ported bus architecture circuits allowing the multiplicity of input/output devices to simultaneously present all input/output data to both central processor units thereby enabling both of said central processor units to receive and process the same data concurrently; encircuiting means providing each of said central processor units with a watch dog timer for continuously monitoring the operational performance of its associated central processor unit, each watch dog timer including provision for repetitiously monitoring the ability of its associated central processor unit to properly decode a periodically sent predetermined message sequence, an improper result signifying a malfunction, said watch dog timer for the central processor unit functioning as "Master" further having the capability to transfer control of said remote multiplexer terminal to the "Slave" central processor unit when said "Master" malfunctions; and parallel linkage means between the dual central processor units serving to transfer control over all input/output functions without delay or loss of data when failover occurs on the malfunction of the first or "Master" central processor unit.
Claim 2
Dependent Claim
272 words
Apparatus for providing a remote multiplexer terminal with a failover capability from a first central processor unit to a second central processor unit without loss of data, said remote multiplexer terminal being a data acquisition and control system capable of receiving data at a clocked rate from a multiplicity of input/output devices and after processing that data according to a software program, delivering the results to an external equipment, the software program additionally serving to designate the first central processor unit as the "Master" and the second central processor unit as the "Slave", the apparatus being integral with the central processor units and comprising: dual ported bus architecture circuits allowing the multiplicity of input/output devices to simultaneously present all input/output data to both central processor units thereby enabling both of said central processor units to receive and process the same data concurrently; encircuiting means providing each of said central processor units with a watch dog timer for continuously monitoring the operational performance of its associated central processor unit, each watch dog timer including provision for repetitiously monitoring the ability of its associated central processor unit to properly decode a periodically sent predetermined message sequence, an improper result signifying a malfunction, said watch dog timer for the central processor unit functioning as "Master" further having the capability to transfer control of said remote multiplexer terminal to the "Slave" central processor unit when said "Master" malfunctions; and parallel linkage means between the dual central processor units serving to transfer control over all input/output functions without delay or loss of data when failover occurs on the malfunction of the first or "Master" central processor unit.
Claim 3
Dependent Claim
42 words
The invention as defined in claim 1 wherein each of said first and second central processor units comprises a printed circuit board assembly which includes and encircuits a microprocessor, a system timing controller, an interrupt controller and a CPU-to-CPU parallel link module.
Claim 4
Dependent Claim
15 words
The invention as defined in claim 3 wherein the microprocessor is a 16 bit unit.
Claim 5
Dependent Claim
34 words
The invention as defined in claim 2 and including linkages connecting the CPU-to-CPU parallel link module of said first central processor unit with the CPU-to-CPU parallel link module of said second central processor unit.
Claim 6
Dependent Claim
20 words
The invention as defined in claim 2 wherein the system timing controller is a software programmable multiple counter integrated circuit.
Claim 7
Dependent Claim
20 words
The invention as defined in claim 5 wherein the watch dog counter comprises one section of the system timing controller.