Patent US5166085A successfully refreshed from Google Patents.
US5166085A
Expired / Lapsed
US
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Method of manufacturing a thin film transistor
Assignee: Casio Computer Co Ltd
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Filing: 1990-04-02
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Granted: 1992-11-24
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Expires: 2010-04-02
Abstract
Abstract First, a gate metal layer, a gate insulating film, a semiconductor layer, an n-type semiconductor layer, and an ohmic metal layer formed on a substrate in the order mentioned. Then, the film and the layers are patterned into those having the same shape and size. Next, a source metal layer and a drain metal layer are formed on the ohmic metal layer. Further, a portion of the ohmic metal layer, a portion of said source metal layer, and a portion of said drain metal layer are etched, thereby forming a channel portion. Finally, a transparent electrode is formed on the source metal layer, thus manufacturing a TFT. Since the film and the layer, the major components of the TFT, are sequentially formed, and are patterned simultaneously, the TFT can be manufacture with high yield. Further, since the transparent electrode is formed on the uppermost layer, i.e., the source metal layer, the pixel has a great opening ratio.
Inventors
- 👤 Haruo Wakai
- 👤 Nobuyuki Yamamura
- 👤 Syunichi Sato
- 👤 Minoru Kanbara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/674; H10D86/00; G02F1/1333; G02F1/133357; G02F1/136227
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
141 words
A method of manufacturing a TFT comprising the steps of: forming and stacking sequentially, on a substrate, a gate metal layer, a gate insulating film, a semiconductor layer, and an n-type semiconductor layer, in the order mentioned; patterning said gate metal layer, said gate insulating film, said semiconductor layer, and said n-type semiconductor layer into those having the same shape and size by means of successive etching in a same processing step; forming an insulating film on said substrate, surrounding said film and layers thus patterned; forming a source electrode and a drain electrode above said n-type semiconductor layer by means of etching a metal layer; etching a portion of said n-type semiconductor layer, a portion of said source electrode, and a portion of said drain electrode, thereby forming a channel portion; and forming a transparent electrode on said source electrode.
Claim 2
Independent Claim
141 words
A method of manufacturing a TFT comprising the steps of: forming and stacking sequentially, on a substrate, a gate metal layer, a gate insulating film, a semiconductor layer, and an n-type semiconductor layer, in the order mentioned; patterning said gate metal layer, said gate insulating film, said semiconductor layer, and said n-type semiconductor layer into those having the same shape and size by means of successive etching in a same processing step; forming an insulating film on said substrate, surrounding said film and layers thus patterned; forming a source electrode and a drain electrode above said n-type semiconductor layer by means of etching a metal layer; etching a portion of said n-type semiconductor layer, a portion of said source electrode, and a portion of said drain electrode, thereby forming a channel portion; and forming a transparent electrode on said source electrode.
Claim 3
Dependent Claim
26 words
The method according to claim 1, wherein said semiconductor layer is made of amorphous silicon, and said n-type semiconductor layer is made of n-type amorphous silicon.
Claim 4
Dependent Claim
14 words
The method according to claim 1, wherein said transparent electrode is a pixel electrode.
Claim 5
Dependent Claim
31 words
The method according to claim 1, wherein said insulating film has a thickness which is equal to or greater than the thickness of said gate metal layer formed on said substrate.
Claim 6
Dependent Claim
29 words
The method according to claim 4, wherein the thickness of said insulating film is equal to or greater than the height of said n-type semiconductor layer above said substrate.
Claim 7
Independent Claim
162 words
A method of manufacturing a TFT comprising: a first step of forming and stacking sequentially, on a substrate, a gate metal layer, a gate insulating film, a semiconductor layer, and an n-type semiconductor layer, in the order mentioned; a second step of patterning said gate metal layer, said gate insulating film, said semiconductor layer, and said n-type semiconductor layer into those having the same shape and size by means of successive etching in a same processing step; a third step of changing a peripheral portion of said gate metal layer to an electrically insulating portion; a fourth step of forming a source electrode and a drain electrode above said n-type semiconductor layer by means of etching a metal layer; a fifth step of etching a portion of said n-type semiconductor layer, a portion of said source electrode, and a portion of said drain electrode, thereby forming a channel portion; and a sixth step of forming a transparent electrode on said source electrode.
Claim 8
Independent Claim
162 words
A method of manufacturing a TFT comprising: a first step of forming and stacking sequentially, on a substrate, a gate metal layer, a gate insulating film, a semiconductor layer, and an n-type semiconductor layer, in the order mentioned; a second step of patterning said gate metal layer, said gate insulating film, said semiconductor layer, and said n-type semiconductor layer into those having the same shape and size by means of successive etching in a same processing step; a third step of changing a peripheral portion of said gate metal layer to an electrically insulating portion; a fourth step of forming a source electrode and a drain electrode above said n-type semiconductor layer by means of etching a metal layer; a fifth step of etching a portion of said n-type semiconductor layer, a portion of said source electrode, and a portion of said drain electrode, thereby forming a channel portion; and a sixth step of forming a transparent electrode on said source electrode.
Claim 9
Dependent Claim
26 words
The method according to claim 6, wherein said semiconductor layer is made of amorphous silicon, and said n-type semiconductor layer is made of n-type amorphous silicon.
Claim 10
Dependent Claim
13 words
The method according to claim 6, wherein said third step is anodic oxidation.
Claim 11
Dependent Claim
16 words
The method according to claim 6, wherein said third step is performed after said first step.
Claim 12
Dependent Claim
14 words
The method according to claim 6, wherein said transparent electrode is a pixel electrode.
Claim 13
Independent Claim
201 words
A method of manufacturing a TFT comprising the steps of: the first step of forming a gate electrode on a transparent insulating substrate; the second step of forming a gate insulating film on at least said gate electrode; the third step of forming a semiconductor layer at a position on said gate insulating film corresponding to said gate electrode; the fourth step of stacking a source and a drain electrode on at least a portion of said semiconductor layer corresponding to said gate electrode through an ohmic contact layer so as to be separated from each other by a distance to form a channel portion of said semiconductor layer; the fifth step of forming a transparent insulating film on or above an entire surface of said substrate; the sixth step of forming a through hole in said insulating film above said source electrode; the seventh step of forming a transparent electrode on said insulating film formed in the fifth step so as to be electrically connected to said source electrode through said through hole; and the eighth step of removing at least a portion of said transparent electrode formed in the seventh step located at a position above said channel portion.
Claim 14
Independent Claim
201 words
A method of manufacturing a TFT comprising the steps of: the first step of forming a gate electrode on a transparent insulating substrate; the second step of forming a gate insulating film on at least said gate electrode; the third step of forming a semiconductor layer at a position on said gate insulating film corresponding to said gate electrode; the fourth step of stacking a source and a drain electrode on at least a portion of said semiconductor layer corresponding to said gate electrode through an ohmic contact layer so as to be separated from each other by a distance to form a channel portion of said semiconductor layer; the fifth step of forming a transparent insulating film on or above an entire surface of said substrate; the sixth step of forming a through hole in said insulating film above said source electrode; the seventh step of forming a transparent electrode on said insulating film formed in the fifth step so as to be electrically connected to said source electrode through said through hole; and the eighth step of removing at least a portion of said transparent electrode formed in the seventh step located at a position above said channel portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |