US4601097A
Expired / Lapsed
US
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Method of producing thin-film transistor array
Assignee: Seiko Instruments Inc
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Filing: 1984-10-29
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Granted: 1986-07-22
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Expires: 2004-10-29
Abstract
Abstract A method of manufacturing a thin film transistor array is simplified by processes to form source and drain electrodes at least of ITO film for pixel electrodes on a gate insulating film covering gate electrode and to form islands of an amorphous semiconductor film and a light shield film in the same masking process on the source and the drain electrodes.
Inventors
- 👤 Masafumi Shimbo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:12
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/40; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6723; H10D86/01; H10D86/021; H10D86/0231; H10D86/60; G02F1/1333; G02F1/1335; G02F1/133509; G02F1/133512; G02F2202/00; G02F2202/10; G02F2202/103; H10D86/481
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
276 words
A method of producing a thin-film transistor array comprising: a first step of selectively forming gate electrode wirings as row lines made of a first opaque conductive film on an insulating substrate; a second step of depositing a gate insulator film over said gate electrode wirings and said substrate; a third step of, after depositing at least a first transparent conductive film, selectively forming source electrode wirings as column lines on said gate insulator film and selectively forming drain electrodes at intersecting portions of said gate and source electrode wirings on said gate insulator film and spaced apart from said source electrode wirings, said source electrode wirings and drain electrodes having overlapping portions relative to said gate electrode wirings; a fourth step of depositing an amorphous semiconductor thin film on said source electrode wirings, drain electrodes and gate insulator film; a fifth step of depositing a light-shielding film on said semiconductor thin film; a sixth step of selectively forming islands of said semiconductor thin film and said light-shielding film in the same shape so that each island has said semiconductor thin film at least in contact with a portion of said source electrode wiring, a portion of said drain electrode and a portion of said gate insulator film which is deposited over a portion of said gate electrode wiring; a seventh step of forming contact windows in said gate insulator film at least to expose portions of said gate electrode wirings; and an eighth step of selectively forming at least gate lead-out electrodes of a metal film through said contact windows and source lead-out electrodes of a metal film on portions of said source electrode wirings.
Claim 2
Independent Claim
276 words
A method of producing a thin-film transistor array comprising: a first step of selectively forming gate electrode wirings as row lines made of a first opaque conductive film on an insulating substrate; a second step of depositing a gate insulator film over said gate electrode wirings and said substrate; a third step of, after depositing at least a first transparent conductive film, selectively forming source electrode wirings as column lines on said gate insulator film and selectively forming drain electrodes at intersecting portions of said gate and source electrode wirings on said gate insulator film and spaced apart from said source electrode wirings, said source electrode wirings and drain electrodes having overlapping portions relative to said gate electrode wirings; a fourth step of depositing an amorphous semiconductor thin film on said source electrode wirings, drain electrodes and gate insulator film; a fifth step of depositing a light-shielding film on said semiconductor thin film; a sixth step of selectively forming islands of said semiconductor thin film and said light-shielding film in the same shape so that each island has said semiconductor thin film at least in contact with a portion of said source electrode wiring, a portion of said drain electrode and a portion of said gate insulator film which is deposited over a portion of said gate electrode wiring; a seventh step of forming contact windows in said gate insulator film at least to expose portions of said gate electrode wirings; and an eighth step of selectively forming at least gate lead-out electrodes of a metal film through said contact windows and source lead-out electrodes of a metal film on portions of said source electrode wirings.
Claim 3
Dependent Claim
81 words
The method of producing a thin-film transistor array as claimed in claim 1; wherein, in said third step, a second opaque conductive film is deposited over said first transparent conductive film and both films are selectively etched to form said source electrode wirings and said drain electrodes; and in said sixth step, exposed portions of said second opaque conductive film after forming islands of said semiconductor thin film and said light-shielding film are removed to make said drain electrodes partially transparent.
Claim 4
Dependent Claim
108 words
The method of producing a thin-film transistor array as claimed in claim 2; wherein, an insulator film is deposited over said islands, said gate insulator film, said source electrode wirings and said drain electrodes after said sixth step; said insulator film and/or said gate insulator film are selectively etched in said seventh step to form contact windows by exposing at least portions of said gate electrode wirings and said source electrode wirings using a second resist as a mask; and said gate lead-out electrodes and said source lead-out electrodes are selectively formed in said eighth step by removing said second resist after the deposition of said metal film.
Claim 5
Dependent Claim
108 words
The method of producing a thin-film transistor array as claimed in claim 1; wherein, an insulator film is deposited over said islands, said gate insulator film said source electrode wirings and said drain electrodes after said sixth step; and insulator film and/or said gate insulator film are selectively etched in said seventh step to form contact windows by exposing at least portions of said gate electrode wirings and said source electrode wirings using a second resist as a mask; and said gate lead-out electrodes and said source lead-out electrodes are selectively formed in said eighth step by removing said second resist after the deposition of said metal film.
Claim 6
Independent Claim
344 words
A method of producing a thin-film transistor array comprising: a first step of selectively forming gate electrode wirings as row lines by over-etching of a first opaque conductive film deposited on an insulating substrate using a first resist as a mask, and selectively forming a common electrode by depositing a second transparent conductive film on the first resist and on said substrate and thereafter removing said first resist to expose said gate electrode wirings; a second step of depositing a gate insulator film over said gate electrode wirings, said common electrode and said substrate; a third step of, after depositing at least a first transparent conductive film, selectively forming source electrode wirings as column lines on said gate insulator film and selectively forming drain electrodes at intersecting portions of said gate and source electrode wirings on said gate insulator film and spaced apart from said source electrode wirings, said source electrode wirings and drain electrodes having overlapping portions relative to said gate electrode wirings, and said drain electrodes also having overlapping portions relative to said common electrode with said gate insulating film interposed therebetween to form capacitors; a fourth step of depositing an amorphous semiconductor thin film on said source electrode wirings, drain electrodes and gate insulator film; a fifth step of depositing a light-shielding film on said semiconductor thin film; a sixth step of selectively forming islands of said semiconductor thin film and said light-shielding film in the same shape so that each island has said semiconductors thin film as least in contact with a portion of said source electrode wiring, a portion of said drain electrode and a portion of said gate insulator film which is deposited over a portion of said gate electrode wiring; a seventh step of forming contact windows in said gate insulator film at least to expose portions of said gate electrode wirings; and an eighth step of selectively forming at least gate lead-out electrodes of a metal film through said contact windows and source lead-out electrodes of a metal film on portions of said source electrode wirings.
Claim 7
Independent Claim
344 words
A method of producing a thin-film transistor array comprising: a first step of selectively forming gate electrode wirings as row lines by over-etching of a first opaque conductive film deposited on an insulating substrate using a first resist as a mask, and selectively forming a common electrode by depositing a second transparent conductive film on the first resist and on said substrate and thereafter removing said first resist to expose said gate electrode wirings; a second step of depositing a gate insulator film over said gate electrode wirings, said common electrode and said substrate; a third step of, after depositing at least a first transparent conductive film, selectively forming source electrode wirings as column lines on said gate insulator film and selectively forming drain electrodes at intersecting portions of said gate and source electrode wirings on said gate insulator film and spaced apart from said source electrode wirings, said source electrode wirings and drain electrodes having overlapping portions relative to said gate electrode wirings, and said drain electrodes also having overlapping portions relative to said common electrode with said gate insulating film interposed therebetween to form capacitors; a fourth step of depositing an amorphous semiconductor thin film on said source electrode wirings, drain electrodes and gate insulator film; a fifth step of depositing a light-shielding film on said semiconductor thin film; a sixth step of selectively forming islands of said semiconductor thin film and said light-shielding film in the same shape so that each island has said semiconductors thin film as least in contact with a portion of said source electrode wiring, a portion of said drain electrode and a portion of said gate insulator film which is deposited over a portion of said gate electrode wiring; a seventh step of forming contact windows in said gate insulator film at least to expose portions of said gate electrode wirings; and an eighth step of selectively forming at least gate lead-out electrodes of a metal film through said contact windows and source lead-out electrodes of a metal film on portions of said source electrode wirings.
Claim 8
Dependent Claim
81 words
The method of producing a thin-film transistor array as claim in claim 5; wherein, in said third step, a second opaque conductive film is deposited over said first transparent conductive film and both films are selectively etched to form said source electrode wirings and said drain electrodes; and in said sixth step, exposed portions of said second opaque conductive film after forming islands of said semiconductor thin film and said light-shielding film are removed to make said drain electrodes partially transparent.
Claim 9
Dependent Claim
108 words
The method of producing a thin-film transistor array as claimed in claim 5; wherein, an insulator film is deposited over said islands, said gate insulator film, said source electrode wirings and said drain electrodes after said sixth step; said insulator film and/or said gate insulator film are selectively etched in said seventh step to form contact windows by exposing at least portions of said gate electrode wirings and said source electrode wirings using a second resist as a mask; and said gate lead-out electrodes and said source lead-out electrodes are selectively formed in said eighth step by removing said second resist after the deposition of said metal film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |