US5159686A
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Multi-processor computer system having process-independent communication register addressing
Assignee: HP Inc
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Filing: 1991-03-07
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Granted: 1992-10-27
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Expires: 2011-03-07
Abstract
Abstract A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available. However, if all processors are busy, then the processor conducting the serial operation will also execute all of the parallel operations. Thus, the processors are self-allocated, rather than being used on a demand or master-servant basis. This permits a greater throughput for the system because processors are not held idle when there is available process work to be done.
Inventors
- 👤 David M. Chastain
- 👤 James E. Mankovich
- 👤 Gary B. Gostin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/50; G06F9/5061; G06F9/5066; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F15/76; G06F15/80; G06F15/8053; G06F9/52
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
362 words
A computer system having multiple processors for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective communication index register associated with each of said processors, each of said communication index registers for storing a process-independent communication index register value therein which comprises a first address segment and serves to address one of said communication register sets, wherein said communication index register values are not set or read by instructions in said process, a respective logic circuit associated with each of said processors for producing a second address segment which is derived form the execution of instructions in said process, wherein said second address segment serves as an address for one of the registers in each of said communication register sets, bus circuits connected to said communication registers, said semaphore registers, said communication index registers and said logic circuits for conveying addresses and data associated with said communication registers and said semaphore registers, an address circuit connected via one or more of said bus circuits to said communication index registers and said logic circuits for receiving said first and second address segments and producing therefrom a composite address which corresponds to one of the registers within one of said communication register sets, wherein a first of said processors when encountering a parallelization instruction during execution of said process communicates via one or more of said bus circuits with a selected one of said communication register sets by use of at least said process-independent first address segment to store process state information therein and to set a state of the associated semaphore register, and a second of said processors is connected via one or more of said bus circuits to communicate with said selected one communication register set by use of at least said process-independent first address segment to scan the state of the associated semaphore register and to read said process state information therefrom when the semaphore register is set so that said first and second processors can execute said process in parallel.
Claim 2
Dependent Claim
362 words
A computer system having multiple processors for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective communication index register associated with each of said processors, each of said communication index registers for storing a process-independent communication index register value therein which comprises a first address segment and serves to address one of said communication register sets, wherein said communication index register values are not set or read by instructions in said process, a respective logic circuit associated with each of said processors for producing a second address segment which is derived form the execution of instructions in said process, wherein said second address segment serves as an address for one of the registers in each of said communication register sets, bus circuits connected to said communication registers, said semaphore registers, said communication index registers and said logic circuits for conveying addresses and data associated with said communication registers and said semaphore registers, an address circuit connected via one or more of said bus circuits to said communication index registers and said logic circuits for receiving said first and second address segments and producing therefrom a composite address which corresponds to one of the registers within one of said communication register sets, wherein a first of said processors when encountering a parallelization instruction during execution of said process communicates via one or more of said bus circuits with a selected one of said communication register sets by use of at least said process-independent first address segment to store process state information therein and to set a state of the associated semaphore register, and a second of said processors is connected via one or more of said bus circuits to communicate with said selected one communication register set by use of at least said process-independent first address segment to scan the state of the associated semaphore register and to read said process state information therefrom when the semaphore register is set so that said first and second processors can execute said process in parallel.
Claim 3
Dependent Claim
33 words
A computer system having multiple processors as recited in claim 1 wherein said logic circuit comprises an arithmetic logic unit which responds to said process instructions to generate said second address segment therefrom.
Claim 4
Dependent Claim
426 words
A computer system having multiple processors for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective communication index register associated with each of said processors, each of said communication index registers for storing a process-independent communication index register value therein which comprises a first address segment and serves to address one of said communication register sets, wherein said communication index register values are not set or read by instructions in said process, a respective logic circuit associated with each of said processors for producing a second address segment which is derived form the execution of instructions in said process, wherein said second address segment serves as an address for one of the registers in each of said communication register sets, bus circuits connected to said communication registers, said semaphore registers, said communication index registers and said logic circuits for conveying addresses and data associated with said communication registers and said semaphore registers, an address circuit connected via one or more of said bus circuits to said communication index registers and said logic circuits for receiving said first and second address segments and producing therefrom a composite address which corresponds to one of the registers within one of said communication register sets, wherein a first of said processors when encountering a parallelization instruction during execution of said process communicates via one or more of said bus circuits with a selected one of said communication register sets by use of at least said process-independent first address segment to store process state information therein and to set a state of the associated semaphore register, and a respective microcode operation circuit associated with each of said processors, said microcode operation circuit connected to the communication index register for the corresponding processor to periodically increment the value stored therein when the corresponding processor is in an idle state, and said microcode operation circuit is further connected to read said semaphore registers by use of at least said first address segment, and a second of said processors is connected via one of more of said bus circuits to communicate with said selected one communication register set by use of at least said process-independent first address segment to scan the state of the associated semaphore register and to read said processor state information therefrom when the semaphore register is set so that said first and second processors can execute said process in parallel.
Claim 5
Dependent Claim
426 words
A computer system having multiple processors for parallel execution of a process, comprising: a plurality of communication register sets, each set comprising a plurality of communication registers, at least one respective semaphore register associated with one register in each of said communication register sets, a respective communication index register associated with each of said processors, each of said communication index registers for storing a process-independent communication index register value therein which comprises a first address segment and serves to address one of said communication register sets, wherein said communication index register values are not set or read by instructions in said process, a respective logic circuit associated with each of said processors for producing a second address segment which is derived form the execution of instructions in said process, wherein said second address segment serves as an address for one of the registers in each of said communication register sets, bus circuits connected to said communication registers, said semaphore registers, said communication index registers and said logic circuits for conveying addresses and data associated with said communication registers and said semaphore registers, an address circuit connected via one or more of said bus circuits to said communication index registers and said logic circuits for receiving said first and second address segments and producing therefrom a composite address which corresponds to one of the registers within one of said communication register sets, wherein a first of said processors when encountering a parallelization instruction during execution of said process communicates via one or more of said bus circuits with a selected one of said communication register sets by use of at least said process-independent first address segment to store process state information therein and to set a state of the associated semaphore register, and a respective microcode operation circuit associated with each of said processors, said microcode operation circuit connected to the communication index register for the corresponding processor to periodically increment the value stored therein when the corresponding processor is in an idle state, and said microcode operation circuit is further connected to read said semaphore registers by use of at least said first address segment, and a second of said processors is connected via one of more of said bus circuits to communicate with said selected one communication register set by use of at least said process-independent first address segment to scan the state of the associated semaphore register and to read said processor state information therefrom when the semaphore register is set so that said first and second processors can execute said process in parallel.
Claim 6
Dependent Claim
64 words
A computer system having multiple processors as recited in claim 3 including at least a second semaphore register associated with each of said communication register sets and connected via one or more of said bus circuits so that said second semaphore register can be set by one of said processors to prevent access to the corresponding communication register set by other of said processors.
Claim 7
Dependent Claim
33 words
A computer system having multiple processors as recited in claim 3 wherein said logic circuit comprises an arithmetic logic unit which responds to said process instructions to generate said second address segment therefrom.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-27 | 1996-04-27 | 1996-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-27 | 2000-04-27 | 2000-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-27 | 2004-04-27 | 2004-10-27 | $7700.00 | Window Closed / Lapsed |