US4704680A
Expired / Lapsed
US
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Address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle
Assignee: St Clair Intellectual Property Consultants Inc
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Filing: 1984-08-15
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Granted: 1987-11-03
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Expires: 2004-08-15
Abstract
Abstract An address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle. A first set of registers is provided for storing starting addresses for each array. A second set of registers is provided for storing current addresses for each array. Logic is provided for initially providing, at the beginning of a series of computation steps to be executed repetitively, an address from a register in the first set of registers, changing that address, and storing it back in the same register and in a corresponding register in the second set, thereby updating the starting address for the next repetition of those computational steps while advancing the current address to the second of those steps.
Inventors
- 👤 Charles L. Saxe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:58
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/345
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
220 words
An address computation system for updating starting addresses of data arrays in an array processor having a data memory and means for executing an operational instruction during an instruction cycle, comprising: (a) first address register means for storing a predetermined portion of a starting data address to be provided to said data memory; (b) second address register means for storing a predetermined portion of a current data address to be provided to said data memory; (c) output multiplexer means, responsive to the outputs of said first and second address register means and to an operational instruction, for selectively presenting to the data memory either said starting data address portion or said current data address portion; and (d) update combinational logic means, responsive to the output of said first address register means and to an operational instruction, for changing said starting data address portion by a predetermined amount to provide a changed data address portion as it is being presented to the data memory and loading said changed data address portion into both said first and second address means for storage therein, said changing and loading occurring within one instruction cycle of said data processing apparatus, whereby new current addresses and new starting addresses are computed with each successive pass through a computation sequence so as to maximize array processing speed.
Claim 2
Dependent Claim
220 words
An address computation system for updating starting addresses of data arrays in an array processor having a data memory and means for executing an operational instruction during an instruction cycle, comprising: (a) first address register means for storing a predetermined portion of a starting data address to be provided to said data memory; (b) second address register means for storing a predetermined portion of a current data address to be provided to said data memory; (c) output multiplexer means, responsive to the outputs of said first and second address register means and to an operational instruction, for selectively presenting to the data memory either said starting data address portion or said current data address portion; and (d) update combinational logic means, responsive to the output of said first address register means and to an operational instruction, for changing said starting data address portion by a predetermined amount to provide a changed data address portion as it is being presented to the data memory and loading said changed data address portion into both said first and second address means for storage therein, said changing and loading occurring within one instruction cycle of said data processing apparatus, whereby new current addresses and new starting addresses are computed with each successive pass through a computation sequence so as to maximize array processing speed.
Claim 3
Dependent Claim
71 words
The system of claim 1 wherein said predetermined portions of said starting and current data addresses comprise a predetermined number of least significant bits of multiple-bit binary addresses, said system further comprising third address register means for storing the remaining bits of said binary addresses and means responsive to the outputs of said third register means and said output multiplexer means for presenting a complete binary address to the data memory.
Claim 4
Dependent Claim
31 words
The system of claim 1 wherein said update logic unit includes means for changing said current data address portion by a predetermined amount to provide a second changed data address portion.
Claim 5
Dependent Claim
90 words
The system of claim 1 wherein said update logic unit includes arithmetic logic means for selectively performing arithmetic or logic operations on either or both of two input operands and producing a result, first intermediate multiplexer means for providing as one openand input to said arithmetic logic means said first data address portion from said first address register means, means for providing as a second operand input to said arithmetic logic means a predetermined value, and means for storing said result into one or both of said address register means.
Claim 6
Dependent Claim
48 words
The system of claim 4 wherein said means for providing a predetermined value comprises an offset register means for storing said predetermined value and a second intermediate multiplexer means for selecting as an input operand to said arithmetic logic means the value stored in said offset register means.
Claim 7
Dependent Claim
72 words
The system of claim 5 wherein said second intermediate multiplexer means is responsive to said second address register means for selecting as an input to said arithmetic logic means said current data address portion stored in said second address register means, and said first intermediate multiplexer means is responsive to said offset register means for selecting as an input to said arithmetic logic means the value stored in said offset register means.
Claim 8
Dependent Claim
35 words
The system of claim 1 wherein said first and second address register means each comprise a plurality of storage registers and means for selectively storing in or reading from those storage registers an address portion.
Claim 9
Dependent Claim
87 words
The system of claim 7 wherein the portions of data addresses stored in said first and second address register means comprise a predetermined number of the least significant bits of respective binary addresses, said system further comprising a third plurality of storage registers for storing the remaining bits of said binary addresses, means for selectively storing in or reading from the third storage registers, and means responsive to the third storage registers and said output multiplexer means for presenting a complete binary address to the data memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-02 | 1991-05-04 | 1991-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-02 | 1995-05-04 | 1995-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-02 | 1999-05-04 | 1999-11-03 | $7700.00 | Window Closed / Lapsed |