Multiprocessor computer system comprising n parallel operating computer modules, and computer module for use in such a multiprocessor computer system

Claim 1

A multiprocessor computer system, comprising n synchronously controlled parallel operating computer modules, each of which is localized in its own fault isolation area, each computer module comprising: a processor module; a data channel which is connected to a data connection of the processor module; a reducing encoder which is connected to the data channel in order to form a code symbol from a data word received from said data channel so that said encoders of the modules processing said data word form, on the basis of a data word comprising k data symbols, a code word consisting of k+1≦n<3k code symbols of a code incorporating a simultaneous correction capability in at least two code symbols; a memory module comprising a first data input which is connected to a first data output of the associated reducing encoder, and to a relevant second data output of each memory module of the respective computer modules; and a data word reconstruction module which is connected via an interconnection network, to the relevant second data outputs of the memory modules of the various computer modules in order to receive a relevant code symbol of a code word from each computer module in order to construct a data word therefrom, the data word reconstruction module comprising a third data output which is connected to said data connection and to said data channel, said data channel also comprising a second data connection for external data input/output, wherein each computer module further comprises: a second data channel which is connected in series with said second data connection and which comprises a third data connection; an input/output memory module which is connected, at least when a generator matrix (G i ) of the associated reducing encoder maps a data bit on more than one code bit to the second data channel by way of a second nonreducing encoder and a third data input and a decoder which is associated with the second encoder, the following relations existing between the generator matrix (G i ) of a reducing encoder, at least in so far as this encoder maps a data bit on more than one code bit, the generator matrix (G i *) of the second encoder, and the generator matrix (G i * -1 ) of the decoder: [G.sub.i *]·[G.sub.i *.sup.-1 ]=[I], the identity matrix; [F]=[G.sub.i ]·[G.sub.i *.sup.-1 ], in which each column of [F] written as consisting of bits, comprises at the most one "1" and for the remainder exclusively "zeroes", each row of [F] containing at least one "1", so that in the relevant computer module a bit of a data word encoded in the input/output memory is mapped on at the most one bit of the code symbol which can be formed from that data word.