Multi-processor system

Claim 2

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with each slave processor having access only to a respective slave memory and with the master processor having access both to the master memory and to all of the slave memories; a common bus shared by all of said processors; each processor having its own address/data bus connecting it to its respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor; each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle; and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and at any time to disable the access by any selected slave processor to its respective memory for no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

Claim 3

A data processing system in accordance with claim 1 wherein said master processor synchronizes the phase clock signals in said slave processors by applying less than all of its phase clock signals to said common bus together with a control clock signal whose frequency is higher than those of all of said phase clock signals.

Claim 4

A data processing system in accordance with claim 2 wherein said master processor generates interruptable phase clock signals but applies none of them to said common bus and, in addition to said higher clock frequency, said master processor applies to said common bus a continuous clock signal which has a frequency equal to that of one of its interruptable phase clock signals.

Claim 5

A data processing system in accordance with claim 3 wherein all of said processors are identical in configuration and each can function as either the master or a slave, and each of said processors includes hardware connection means for determining whether the processor functions as a master or a slave.

Claim 6

A data processing system in accordance with claim 1 wherein the control means in a selected slave processor suspends the generation of phase clock signals while the master processor is accessing the respective slave memory and then allows them to be generated again at the end of the cycle during which said master processor accesses the respective slave memory, all of the other slave processors continuing to generate their own phase clock signals to enable accesses to their respective memories while said master processor accesses said respective slave memory.

Claim 7

A data processing system in accordance with claim 1 wherein all of said processors are identical in configuration and each can function as either the master or a slave, and each of said processors includes hardware connection means for determining whether the processor functions as a master or a slave.

Claim 8

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with the master processor having access both to the master memory and to at least two of the slave memories; a common bus; each processor having its own address/data bus connecting it to a respective memory, and said master processor and the at least two slave processors associated with said at least two slave memories having means connected to said common bus for controlling said master processor to transmit address and data signals to said at least two slave memories and for controlling said at least two slave memories to transmit data signals to said master processor; each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle; and control means in said master processor and in each of said at least two slave processors, connected over said common bus, for disabling at any time the access by any selected one of said at least two slave processors to its respective memory while said master processor accesses such respective slave memory for no longer than the single processor cycle during which such master processor access takes place and said selected slave processor would otherwise access such respective slave memory.

Claim 9

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with the master processor having access both to the master memory and to at least two of the slave memories; a common bus; each processor having its own address/data bus connecting it to a respective memory, and said master processor and the at least two slave processors associated with said at least two slave memories having means connected to said common bus for controlling said master processor to transmit address and data signals to said at least two slave memories and for controlling said at least two slave memories to transmit data signals to said master processor; each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle; and control means in said master processor and in each of said at least two slave processors, connected over said common bus, for disabling at any time the access by any selected one of said at least two slave processors to its respective memory while said master processor accesses such respective slave memory for no longer than the single processor cycle during which such master processor access takes place and said selected slave processor would otherwise access such respective slave memory.

Claim 10

A data processing system in accordance with claim 7 further comprising means for synchronizing said at least two slave processors to said master processor, said synchronizing means including means in said master processor for applying less than all of its phase clock signals to said common bus together with a control clock signal whose frequency is higher than those of all of said phase clock signals, and means in each of said at least two slave processors for operating on said applied signals to control the generation of all of said phase clock signals.

Claim 11

A data processing system in accordance with claim 8 wherein said master processor generates interruptable phase clock signals but applies none of them to said common bus and, in addition to said control clock signal, said master processor applies to said common bus a continuous clock signal which has a frequency equal to that of one of its interruptable phase clock signals.

Claim 12

A data processing system in accordance with claim 7 wherein the control means in a selected slave processor suspends the generation of phase clock signals while the master processor is accessing the respective slave memory and then causes them to be generated again at the end of the cycle during which said master processor accesses the respective slave memory, all of the other slave processors continuing to generate their own phase clock signals to enable accesses to their respective memories while said master processor accesses said respective slave memory.

Claim 13

A data processing system in accordance with claim 7 wherein all of said processors are identical in configuration and each can function as either the master or a slave, and each of said processors includes hardware connection means for determining whether the processor functions as a master or a slave.

Claim 14

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with the master processor having access to the master memory and priority access to all of the slave memories; a common bus shared by all of said processors; each processor having its own address/data bus connecting it to a respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor; each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle; and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and to inhibit at any time the access by any selected slave processor to its respective memory during no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

Claim 15

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with the master processor having access to the master memory and priority access to all of the slave memories; a common bus shared by all of said processors; each processor having its own address/data bus connecting it to a respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor; each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle; and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and to inhibit at any time the access by any selected slave processor to its respective memory during no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

Claim 16

A data processing system in accordance with claim 12 wherein said master processor synchronizes the phase clock signals in said slave processors by applying less than all of its phase clock signals to said common bus together with a control clock signal whose frequency is higher than those of all of said phase clock signals.

Claim 17

A data processing system in accordance with claim 13 wherein said master processor generates interruptable phase clock signals but applies none of them to said common bus and, in addition to said higher clock frequency, said master processor applies to said common bus a continuous clock signal which has a frequency equal to that of one of its interruptable phase clock signals.

Claim 18

A data processing system in accordance with claim 14 wherein all of said processors are identical in configuration and each can function as either the master or a slave, and each of said processors includes hardware connection means for determining whether the processor functions as a master or a slave.

Claim 19

A data processing system in accordance with claim 12 wherein the control means in a selected slave processor suspends the generation of phase clock signals while the master processor is accessing the respective slave memory and then causes them to be generated again at the end of a master processor cycle during which said master processor accesses the respective slave memory, all of the other slave processors continuing to generate their own phase clock signals under control of said master processor to enable accesses to their respective memories while said master processor accesses said respective slave memory.

Claim 20

A data processing system in accordance with claim 12 wherein all of said processors are identical in configuration and each can function as either the master or a slave, and each of said processors includes hardware means for determining whether the processor functions as a master or a slave.

Claim 21

A data porcessing system in accordance with claim 17 wherein the determining means in each of said processors includes a signal line whose potential determines whether the processor functions as a master or a slave; and wherein each of said processors is contained on a respective circuit card with all of the circuit cards being inserted in a backplane which carries said common bus, said backplane including means for applying selected potentials to all of said determining means signal lines to control which of said processors functions as a master with the others functioning as slaves.

Claim 22

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with each slave processor having access to a respective slave memory and with the master processor having access to both the master memory and to all of the slave memories; a common bus shared by all of said processors; each processor having its own address/data bus connecting it to its respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor; each of said processors including clock-generating means for generating two phase clock signals to enable an access to its respective memory during a respective processor cycle, the processor outputting address signals during the first of said phase clock signals and a memory operation then taking place during the second of said phase clock signals; and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and to disable at any time the access by any selected slave processor to its respective memory for no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

Claim 23

A data processing system having a master processor and at least two slave processors; a master memory and a plurality of slave memories, with each slave processor having access to a respective slave memory and with the master processor having access to both the master memory and to all of the slave memories; a common bus shared by all of said processors; each processor having its own address/data bus connecting it to its respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor; each of said processors including clock-generating means for generating two phase clock signals to enable an access to its respective memory during a respective processor cycle, the processor outputting address signals during the first of said phase clock signals and a memory operation then taking place during the second of said phase clock signals; and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and to disable at any time the access by any selected slave processor to its respective memory for no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

Claim 24

A data processing system in accordance with claim 19 wherein the control means in each slave processor allows the outputting of address signals by the slave processor to its respective memory during the first of said phase clock signals even if during a particular processor cycle an access is to be made to the respective slave memory by the master processor; the control means, in the event of such an access, then inhibiting the generation of the second phase clock signal of said particular processor cycle and the first phase clock signal of the next processor cycle so that the operation on the slave memory in accordance with the outputted address signals takes place during the second phase clock signal of said next processor cycle.

Claim 25

A data processing system in accordance with claim 20 wherein said memories are dynamic semiconductor memories and said master processor further includes means for controlling a simultaneous refresh operation in all of said memories by suspending the generation of both phase clock signals by every processor for a single processor cycle; and wherein the control means in each slave processor, responsive to an access to the respective slave memory by the master processor followed by a refresh operation, inhibits the generation of the second phase clock signal of said next processor cycle and the generation of the first phase clock signal of the succeeding processor cycle so that the operation on the slave memory in accordance with the outputted address signals takes place during the second phase clock signal of said succeeding processor cycle.

Claim 26

A data processing system in accordance with claim 21 wherein each of said processors includes a microprocessor selected from a 6800-series chip set.

Claim 27

A data processing system in accordance with claim 22 wherein each of said clock-generating means is a 6875 clock generator.

Claim 28

A data processing system having a master processor, a first memory and at least two second memories; with said first memory being accessed by said master processor specifying an address in a first address space and said at least two second memories being accessed by said master processor specifying an address in a second, different, address space; address and data buses connected between said master processor and all of said memories; register means, settable by said master processor, for selectively identifying a particular one of said second memories; means connected to said first memory and said at least two second memories and said address and data buses, responsive to said master processor specifying an address in said second address space for accessing the particular one of said second memories identified by said register means; whereby, following setting of said register means by said master processor, said master processor can access said first memory or the identified particular second memory by specifying a respective address in said first or second address space without requiring a subsequent setting of said register means until such time that access by said master processor to another of said second memories is required; said register means being set by said master processor specifying an address which is in neither of said first and second address spaces, with said register means being set to identify a particular one of said second memories in accordance with data appearing on said data bus; and a plurality of additional processors each for accessing a respective one of said second memories by specifying an address in said second address space.

Claim 29

A data processing system having a master processor, a first memory and at least two second memories; with said first memory being accessed by said master processor specifying an address in a first address space and said at least two second memories being accessed by said master processor specifying an address in a second, different, address space; address and data buses connected between said master processor and all of said memories; register means, settable by said master processor, for selectively identifying a particular one of said second memories; means connected to said first memory and said at least two second memories and said address and data buses, responsive to said master processor specifying an address in said second address space for accessing the particular one of said second memories identified by said register means; whereby, following setting of said register means by said master processor, said master processor can access said first memory or the identified particular second memory by specifying a respective address in said first or second address space without requiring a subsequent setting of said register means until such time that access by said master processor to another of said second memories is required; said register means being set by said master processor specifying an address which is in neither of said first and second address spaces, with said register means being set to identify a particular one of said second memories in accordance with data appearing on said data bus; and a plurality of additional processors each for accessing a respective one of said second memories by specifying an address in said second address space.

Claim 30

A data processing system in accordance with claim 24 further including means responsive to simultaneous access attempts to one of said second memories by said master processor and the respective one of said additional processors for giving priority to said master processor and suspending operation of said respective additional processor until after said master processor has accessed said one of said second memories.

Claim 31

A data processing system in accordance with claim 25 further including means for synchronizing the operations of said master processor and said additional processors such that operation of one of said additional processors is suspended for only a single processor cycle during which time the respective one of said second memories is accessed by said master processor.

Claim 32

A data processing system having a master processor, a first memory and at least two second memories; with said first memory being accessed by said master processor specifying an address in a first address space and said at least two second memories being accessed by said master processor specifying an address in a second, different, address space; address and data buses connected between said master processor and all of said memories; register means, settable by said master processor, for selectively identifying a particular one of said second memories; means connected to said first memory and said at least two second memories and said address and data buses, responsive to said master processor specifying an address in said second address space for accessing the particular one of said second memories identified by said register menas; whereby, following setting of said register means by said master processor, said master processor can access said first memory or the identified particular second memory by specifying a respective address in said first or second address space without requiring a subsequent setting of said register means until such time that access by said master processor to another of said second memories is required; and a plurality of additional processors each for accessing a respective one of said second memories by specifying an address in said second address space.

Claim 33

A data processing system having a master processor, a first memory and at least two second memories; with said first memory being accessed by said master processor specifying an address in a first address space and said at least two second memories being accessed by said master processor specifying an address in a second, different, address space; address and data buses connected between said master processor and all of said memories; register means, settable by said master processor, for selectively identifying a particular one of said second memories; means connected to said first memory and said at least two second memories and said address and data buses, responsive to said master processor specifying an address in said second address space for accessing the particular one of said second memories identified by said register menas; whereby, following setting of said register means by said master processor, said master processor can access said first memory or the identified particular second memory by specifying a respective address in said first or second address space without requiring a subsequent setting of said register means until such time that access by said master processor to another of said second memories is required; and a plurality of additional processors each for accessing a respective one of said second memories by specifying an address in said second address space.

Claim 34

A data processing system in accordance with claim 27 further including means responsive to simultaneous access attempts to one of said second memories by said master processor and the respective one of said additional processors for giving priority to said master processor and suspending operation of said respective additional processor until after said master processor has accessed said one of said second memories.

Claim 35

A data processing system in accordance with claim 28 further including means for synchronizing the operations of said master processor and said additional processors such that operation of one of said additional processors is suspended for only a single processor cycle during which time the respective one of said second memories is accessed by said master processor.