Control system for a stored program multiprocessor computer

Claim 2

In a stored program computer comprising a plurality of data processors, a common control system comprising: (a) a master controller, operatively connected and responsive to said plurality of data processors, and a plurality of subcontrollers wherein each of said master controller and subcontrollers has a specific function and responsibility for a plurality of said processors and wherein each of said master controller and subcontrollers is autonomous with respect to its function and responsibility; and (b) memory register means for interconnecting said master controller and subcontrollers in a fixed hierarchy of control, said master controller being bilaterally connected to at least one of said subcontrollers through said memory register means, said subcontrollers being bilaterally connected to at least the next least and next most significant subcontrollers in said hierarchy through said memory register means.

Claim 3

The common control system according to claim 1 wherein each controller includes: (a) means for setting bits in the memory register means connecting it to a next lower controller in said hierarchy for the transfer of data, instructions and/or control signals wherein the status of such memory register means causes the next lower controller in the hierarchy to perform its function in a manner specified by the setting; (b) means for setting bits in the memory register means connecting it to a next higher controller in said hierarchy into a status indicating to such higher controller that its function has been completed; and (c) polling means for repeatedly testing the status of said memory register means.

Claim 4

The common control system according to claim 1 including communication register means connecting at least one of said controllers with at least one of said processors and/or input/output devices for communicating control signals between said at least one controller and such processors and/or input/output devices wherein each of such processors and/or input/output devices includes means for setting bits in said communication register means and wherein the polling means of said at least one controller also tests the status of said communication register means.

Claim 5

The common control system according to claim 1 wherein the function of each of said controllers includes scheduling priorities within its specified responsibility for a plurality of said processors.

Claim 6

The common control system according to claim 4 wherein the scheduled priorities are communicated to the next lower controller in the hierarchy by means of the register memory means and wherein the memory register means includes a plurality of registers which are linked in a manner determined by said scheduled priorities.

Claim 7

The common control system according to claim 1 wherein the master controller is the highest controller in the hierarchy and it allocates work among the processors and communicates this allocation to the processors by means of the communication register means.

Claim 8

The common control system according to claim 1 wherein the second highest controller in said hierarchy is a command controller which places sets of instruction groups into a waiting queue which is communicated to the third highest controller in said hierarchy by means of said register memory means.

Claim 9

The common control system according to claim 7 wherein the command controller includes means for allocating memory locations of the central memory upon request.

Claim 10

The common control system according to claim 7 wherein the third controller is a task controller which executes the queue constructed by the command controller and wherein the task controller includes means for breaking down said queues into tasks.

Claim 11

The common control system according to claim 9 wherein the task controller breaks down the tasks in such a manner that the tasks have a predetermined memory space limit and execution time limit.

Claim 12

The common control system according to claim 9 wherein the task controller also includes means for controlling the transfer of data between the central memory and at least one additional memory device.

Claim 13

The common control system according to claim 9 wherein the task controller also includes means for monitoring the flow of tasks through the computer.

Claim 14

The common control system according to claim 1 wherein the fourth controller in the hierarchy is a disc controller which controls the data channel connected to the discs.

Claim 15

The common control system according to claim 13 wherein the disc controller contains means for rearranging requests for use of the data channel connected to the discs.

Claim 16

The common control system according to claim 1 wherein the controllers are stored program controllers.

Claim 17

In a stored program computer comprising a plurality of data processors, a common control system comprised of: (a) a master controller, operatively connected and responsive to said plurality of data processors, and a plurality of subcontrollers wherein each of said master controller and subcontrollers has a specific function and responsibility for a plurality of said processors and wherein each of said master controller and subcontrollers is autonomous with respect to this function and responsibility; (b) memory register means for interconnecting said master controller and subcontrollers in a fixed hierarchy of control, said master controller being bilaterally connected to at least one of said subcontrollers through said memory register means, said subcontrollers being bilaterally connected to at least the next least and next most significant subcontrollers in said hierarchy through said memory register means; (c) communication register means operatively connected and responsive to said plurality of processors having a plurality of settable bit positions; and (d) a plurality of input/output devices each including means for setting attention bits in said communication register means to request servicing by one of said plurality of processors wherein at least one of said master controller and subcontrollers schedules processing of data received from one of said input/output devices in a selected one of said processors according to the status of the attention bits set in the communication register and wherein the polling means of said at least one master controller and subcontrollers also tests the status of said communication register means.

Claim 18

In a stored program computer comprising a plurality of data processors, a common control system comprised of: (a) a master controller, operatively connected and responsive to said plurality of data processors, and a plurality of subcontrollers wherein each of said master controller and subcontrollers has a specific function and responsibility for a plurality of said processors and wherein each of said master controller and subcontrollers is autonomous with respect to this function and responsibility; (b) memory register means for interconnecting said master controller and subcontrollers in a fixed hierarchy of control, said master controller being bilaterally connected to at least one of said subcontrollers through said memory register means, said subcontrollers being bilaterally connected to at least the next least and next most significant subcontrollers in said hierarchy through said memory register means; (c) communication register means operatively connected and responsive to said plurality of processors having a plurality of settable bit positions; and (d) a plurality of input/output devices each including means for setting attention bits in said communication register means to request servicing by one of said plurality of processors wherein at least one of said master controller and subcontrollers schedules processing of data received from one of said input/output devices in a selected one of said processors according to the status of the attention bits set in the communication register and wherein the polling means of said at least one master controller and subcontrollers also tests the status of said communication register means.

Claim 19

The common control system according to claim 16 wherein said communication register means includes predetermined availability bits which are set when a processor has reached a break in its processing and wherein the polling means of said at least one controller also tests said availability bits.

Claim 20

The common control system according to claim 16 wherein at least some of said processors are virtual processors which time share an essential part necessary for the functioning of the processors.

Claim 21

The common control system according to claim 18 wherein some of said virtual processors function as controllers.

Claim 22

The common control system according to claim 19 wherein the virtual processors functioning as subcontrollers are selected by a virtual processor functioning as a master controller.

Claim 23

A stored program computer having a plurality of data processors and a central memory coupled to each of said plurality of processors comprising: (a) a common control system for controlling said plurality of data processors; (b) a plurality of peripheral devices including input/output devices; (c) a communication register means having a plurality of memory registers with each memory register having a plurality of individually settable bit positions, at least some of said bit positions designated as attention bits being settable by said input/output devices and at least some of said bit positions being designated availability bits being settable by said plurality of processors; (d) means in said control system for polling said bit positions within said communication register means; and (e) means in said control system for scheduling processing of data from said peripheral devices in dependence upon the status of the bit positions designated the attention bits in said communication register means, said processing routed in selected processors by said control system in dependence upon the status of the bit positions designated the availability bits in said communication register means.

Claim 24

A stored program computer having a plurality of data processors and a central memory coupled to each of said plurality of processors comprising: (a) a common control system for controlling said plurality of data processors; (b) a plurality of peripheral devices including input/output devices; (c) a communication register means having a plurality of memory registers with each memory register having a plurality of individually settable bit positions, at least some of said bit positions designated as attention bits being settable by said input/output devices and at least some of said bit positions being designated availability bits being settable by said plurality of processors; (d) means in said control system for polling said bit positions within said communication register means; and (e) means in said control system for scheduling processing of data from said peripheral devices in dependence upon the status of the bit positions designated the attention bits in said communication register means, said processing routed in selected processors by said control system in dependence upon the status of the bit positions designated the availability bits in said communication register means.

Claim 25

The system according to claim 21 wherein the peripheral devices set predetermined bit positions designated as attention bits to process data from such peripheral devices by one of said processors.

Claim 26

The system according to claim 21 wherein said processors set predetermined bit positions designated as said availability bits when such processors reach a logical break in their processing, thereby indicating to the control system that such processors are available for further assignment of processing.