Patent US5127986A successfully refreshed from Google Patents.
US5127986A
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High power, high density interconnect method and apparatus for integrated circuits
Assignee: Silicon Graphics International Corp
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Filing: 1989-12-01
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Granted: 1992-07-07
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Expires: 2009-12-01
Abstract
Abstract The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive technique. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.
Inventors
- 👤 Melvin C. August
- 👤 Lloyd T. Shepherd
- 👤 James N. Kruchowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:38
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0263; H05K1/0265; H05K3/00; H05K3/40; H05K3/42; H05K3/421; H05K3/422; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/611; H10W70/62; H10W70/66; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H05K1/16; H05K1/162; H05K1/167; H05K2201/00; H05K2201/03; H05K2201/0302; H05K2201/0317; H05K2201/0332; H05K2201/0364; H05K2201/0376; H05K2201/09; H05K2201/09209; H05K2201/0929; H05K2201/09309; H05K2203/00; H05K2203/03; H05K2203/0315; H05K2203/0361; H05K2203/07; H05K2203/0703; H05K2203/072; H05K2203/0733; H05K3/38; H05K3/388; H05K3/46; H05K3/4644; H05K3/4661; H05K3/467; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
127 words
A method of building thick layers in a high power, high density interconnect substrate, comprising: (a) sputtering a first metal onto an underlying metal layer for adhesion, a second metal onto said first metal to act as a catalyst, and a third metal onto said second metal to provide adhesion to a dielectric deposited thereon; (b) etching said first, second, and third metals using photolithography techniques to define a pattern for a fourth metal and covering said underlying metal of the preceding layer; (c) depositing and etching said dielectric using photolithography techniques to define said pattern for said fourth metal; (d) etching said third metal to expose said second metal for depositing said fourth metal thereon; and (e) electroless plating said fourth metal onto said second metal.
Claim 2
Independent Claim
127 words
A method of building thick layers in a high power, high density interconnect substrate, comprising: (a) sputtering a first metal onto an underlying metal layer for adhesion, a second metal onto said first metal to act as a catalyst, and a third metal onto said second metal to provide adhesion to a dielectric deposited thereon; (b) etching said first, second, and third metals using photolithography techniques to define a pattern for a fourth metal and covering said underlying metal of the preceding layer; (c) depositing and etching said dielectric using photolithography techniques to define said pattern for said fourth metal; (d) etching said third metal to expose said second metal for depositing said fourth metal thereon; and (e) electroless plating said fourth metal onto said second metal.
Claim 3
Dependent Claim
32 words
The method of claim 1, wherein the underlying layer comprises copper, the first metal comprises chromium, the second metal comprises palladium, the third metal comprises chromium, and the fourth metal comprises copper.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein said step of depositing and etching said dielectric further comprises vacuum laminating said dielectric.
Claim 5
Dependent Claim
148 words
A circuit board for integrated circuits, comprising at least one high power, high density interconnect substrate, said high power, high density interconnect substrate comprised of thick dielectric and metallization layers, said layers built up by a process comprising the steps of: (a) sputtering a first metal onto an underlying layer for adhesion, a second metal onto said first metal to act as a catalyst, and a third metal onto said second metal to provide adhesion to a dielectric deposited thereon; (b) etching said first, second, and third metals using photolithography techniques to define a pattern for a fourth metal and covering said underlying layer; (c) depositing and etching said dielectric using photolithography techniques to define said pattern for said fourth metal; (d) etching said third metal to expose said second metal for depositing said fourth metal thereon; and (e) electroless plating said fourth metal onto said second metal.
Claim 6
Dependent Claim
148 words
A circuit board for integrated circuits, comprising at least one high power, high density interconnect substrate, said high power, high density interconnect substrate comprised of thick dielectric and metallization layers, said layers built up by a process comprising the steps of: (a) sputtering a first metal onto an underlying layer for adhesion, a second metal onto said first metal to act as a catalyst, and a third metal onto said second metal to provide adhesion to a dielectric deposited thereon; (b) etching said first, second, and third metals using photolithography techniques to define a pattern for a fourth metal and covering said underlying layer; (c) depositing and etching said dielectric using photolithography techniques to define said pattern for said fourth metal; (d) etching said third metal to expose said second metal for depositing said fourth metal thereon; and (e) electroless plating said fourth metal onto said second metal.
Claim 7
Dependent Claim
33 words
The circuit board of claim 4, wherein the underlying layer comprises copper, the first metal comprises chromium, the second metal comprises palladium, the third metal comprises chromium, and the fourth metal comprises copper.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |