EP0083405A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Chip carrier for large scale integrated circuits and a method for the fabrication of the carrier
Assignee: International Business Machines Corp
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Filing: 1982-11-05
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Granted: —
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Expires: 2002-11-05
Abstract
Abstract A carrier for LSI (Large Scale Integration) chips includes a built-in capacitor structure in the carrier. The capacitor is located beneath the chip (11) with the plates (26, 46, 33) of the capacitor parallel to the chip mounting surface (9) or at right angles to the chip mounting surface. The capacitor is formed by assembling an array of capacitive segments (26, 46) together to form the first one of the plates of a capacitor with the other plate (33) spanning a plurality of the segments of the first plate. Each of the segments of the first plate includes a set of conductive via lines (25, 45) which extend up to a severable link (24, 44) on the chip mounting surface. The severable via is cut by means of a laser beam or the like when the capacitor must be repaired by deleting a defective segment of th capacitor. Preferably, the structure includes a pair of parallel conductive charge redistribution planes (22, 35) above and below the capacitor plates with connections to the respective plates providing a low inductance structure achieved by providing a current distribution which results in cancellation of magnetic flux. The lower redistribution plane (35) is preferably connected directly to the lower capacitor plate (33). The upper redistribution plane (22) is preferably connected to the segments (26, 46) of the first capacitor plate by means of the vias (23, 25; 43, 45) which extend first to the chip mounting surface and then down to the redistribution plane which has connections (21) to the chip mounting pads (13).
Inventors
- 👤 Dudley Augustus Chance
- 👤 Gerard Vincent Kopcsay
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:52
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W44/00; H10W44/601; H10W70/67; H10W70/68; H10W70/685; H05; H05K; H05K1/00; H05K1/02; H05K1/0286; H05K1/16; H05K1/162; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
A chip carrier for large scale integrated circuits, comprising an upper surface (9) on which at least one chip (11) is bonded and a capacitor structure located below the chip with the parallel plates of the capacitor structure extending within the body of the carrier, characterized in that the capacitor structure is formed from a plurality of segments (26, 46, 71-76), each segment being electrically connected to a separate connection link (24, 44, 124, 224) on the surface of the carrier, said link being adapted for deletion of the connection between a defective or excessive segment of the capacitor from a circuit in which it is included.
Claim 2
Dependent Claim
107 words
A chip carrier for large scale integrated circuits, comprising an upper surface (9) on which at least one chip (11) is bonded and a capacitor structure located below the chip with the parallel plates of the capacitor structure extending within the body of the carrier, characterized in that the capacitor structure is formed from a plurality of segments (26, 46, 71-76), each segment being electrically connected to a separate connection link (24, 44, 124, 224) on the surface of the carrier, said link being adapted for deletion of the connection between a defective or excessive segment of the capacitor from a circuit in which it is included.
Claim 3
Dependent Claim
41 words
A chip carrier in accordance with claim 1, wherein the capacitor segments are sandwiched between a pair of parallel conductive charge redistribution planes (22, 35) with said segments and said planes extending substantially parallel to the surface (9) of the carrier.
Claim 4
Dependent Claim
119 words
A chip carrier in accordance with claim 1, wherein said capacitor structure comprises one first plate (33) common to all capacitor segments and a plurality of plate segments (26, 46), one for each capacitor segment, said plate segments forming a complementary segmented plate juxtaposed with the first plate and wherein each plate segment (26, 46) is connected by at least one via (23, 25;43, 45) to a corresponding deletable connection link (24, 44), whereby a defective one of said capacitor segments can be eliminated from connection in any circuit in which it is included by means of an externally applied tool applied to the corresponding deletable connection link (24, 44) located on the upper surface (9) of the carrier.
Claim 5
Dependent Claim
28 words
A chip carrier in accordance with claim 3, wherein each of said deletable connection links (24, 44) are connected to a charge redistribution plane (22) within the carrier.
Claim 6
Dependent Claim
32 words
A chip carrier in accordance with claim 4, wherein the charge redistribution plane is located between the upper surface of the carrier and said capacitor plate segments forming said complementary segmented plate.
Claim 7
Dependent Claim
25 words
A chip carrier in accordance with claim 5, wherein a second redistribution plane (35) is located parallel to said plates below the complementary segmented plate.
Claim 8
Dependent Claim
26 words
A chip carrier in accordance with claim 3, wherein said plates (139, 226, 246) are located in planes normal to the upper surface of the carrier.
Claim 9
Dependent Claim
125 words
A chip carrier for large scale integrated circuits, comprising an upper surface (9) on which at least one chip (11) is bounded and a capacitor structure located below the chip with the parallel plates of the capacitor structure extending within the body of the carrier, characterized in that the capacitor structure is formed from at least one segment (26, 46, 71-76), said segment (26) being electrically connected to a chip pad (13) via a first wire (25) extending from the segment to a link (24) on the surface of the carrier, from said link via a second wire (23) aligned with said first wire to a charge redistribution plane (22) and further via a third wire (21) from the redistribution plane to said pad (13).
Claim 10
Dependent Claim
125 words
A chip carrier for large scale integrated circuits, comprising an upper surface (9) on which at least one chip (11) is bounded and a capacitor structure located below the chip with the parallel plates of the capacitor structure extending within the body of the carrier, characterized in that the capacitor structure is formed from at least one segment (26, 46, 71-76), said segment (26) being electrically connected to a chip pad (13) via a first wire (25) extending from the segment to a link (24) on the surface of the carrier, from said link via a second wire (23) aligned with said first wire to a charge redistribution plane (22) and further via a third wire (21) from the redistribution plane to said pad (13).
Claim 11
Independent Claim
111 words
A method of fabrication of a carrier for a chip, characterized by providing a substrate with pins and vias connected to a pair of capacitor plates within said carrier below the surface upon which the chip is mounted, with one of said capacitor plates being broken into segments, with each of said segments having a via connection reaching to the chip mounting surface to connect to a deletable strap connection to another via which connects to means for connection to a chip pad, detecting defects or excess values in said segments of said capacitor, and deleting connections at said straps for segments of said capacitor discovered to be defective, or excessive.
Claim 12
Independent Claim
111 words
A method of fabrication of a carrier for a chip, characterized by providing a substrate with pins and vias connected to a pair of capacitor plates within said carrier below the surface upon which the chip is mounted, with one of said capacitor plates being broken into segments, with each of said segments having a via connection reaching to the chip mounting surface to connect to a deletable strap connection to another via which connects to means for connection to a chip pad, detecting defects or excess values in said segments of said capacitor, and deleting connections at said straps for segments of said capacitor discovered to be defective, or excessive.
References Cited (Backward Citations)
No citation records indexed.
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