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US5089868A
Expired / Lapsed
US
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Semiconductor memory device with improved groove capacitor
Assignee: Mitsubishi Electric Corp
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Filing: 1991-04-02
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Granted: 1992-02-18
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Expires: 2011-04-02
Abstract
Abstract A semiconductor memory device which is provided with a groove type capacitor and which has been improved for increasing its storage capacity without lowering the degree of integration, and the method for producing the memory device. The device includes a first capacitor including a storage node (16) formed on the inner wall of the groove (15), a capacitor insulating film (20) and a cell plate electrode (22), a second capacitor including an electrically conductive member (43) provided on the perimeter of the groove (15), the capacitor insulating film (20) and the cell plate electrode (22). The semiconductor memory device has its storage capacity increased by an amount corresponding to the capacity of the second capacitor. The degree of integration is not lowered in any way since the electrically conductive member (43) forming the second capacitor is provided on the groove (15) perimeter. The method for producing the semiconductor memory device is improved such that high accuracy mask matching is not required during groove (15) formation so that the production efficiency is significantly improved.
Inventors
- 👤 Kaoru Motonami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/377; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0385
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
221 words
A semiconductor memory device for storing information as a function of the presence or absence of electric charges stored in a groove type capacitor, comprising: a semiconductor substrate having a main surface and a groove formed in the main surface, said groove defined by a sidewall surface and a bottom wall surface, a transistor including a gate electrode on said semiconductor substrate and a source/drain impurity diffusion layer formed at the main surface of said semiconductor substrate and at opposite sides of said gate electrode, a first impurity diffusion layer in the sidewall surface and the bottom wall surface of said groove, a second impurity diffusion layer in the main surface of said semiconductor substrate and electrically connecting said first impurity diffusion layer and said source/drain impurity diffusion layer, and a conductive member on said semiconductor substrate and in electrical contact with said second impurity diffusion layer, said conductive member having an opening portion for exposing said groove therethrough, a wall surface defining the opening portion of said conductive member being coplanar with the side wall surface of said groove, and a capacitor insulating film on the side wall surface of said groove and on the wall surface defining the opening portion of said conductive member and covering said conductive member, and a cell plate electrode covering said capacitor insulating film.
Claim 2
Dependent Claim
221 words
A semiconductor memory device for storing information as a function of the presence or absence of electric charges stored in a groove type capacitor, comprising: a semiconductor substrate having a main surface and a groove formed in the main surface, said groove defined by a sidewall surface and a bottom wall surface, a transistor including a gate electrode on said semiconductor substrate and a source/drain impurity diffusion layer formed at the main surface of said semiconductor substrate and at opposite sides of said gate electrode, a first impurity diffusion layer in the sidewall surface and the bottom wall surface of said groove, a second impurity diffusion layer in the main surface of said semiconductor substrate and electrically connecting said first impurity diffusion layer and said source/drain impurity diffusion layer, and a conductive member on said semiconductor substrate and in electrical contact with said second impurity diffusion layer, said conductive member having an opening portion for exposing said groove therethrough, a wall surface defining the opening portion of said conductive member being coplanar with the side wall surface of said groove, and a capacitor insulating film on the side wall surface of said groove and on the wall surface defining the opening portion of said conductive member and covering said conductive member, and a cell plate electrode covering said capacitor insulating film.
Claim 3
Dependent Claim
44 words
A semiconductor memory device according to claim 1, wherein said transistor includes a gate insulating film between said gate electrode and said main surface of said semiconductor substrate, and wherein an edge of said conductive member extends to a position above said gate electrode.
Claim 4
Dependent Claim
45 words
A semiconductor memory device according to claim 1, further comprising an oxide film for separating the elements from one another provided on the main surface of said semiconductor substrate, wherein an outer edge of said conductive member extends to a position above said oxide film.
Claim 5
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein said conductive member surrounds said groove.
Claim 6
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein said conductive member is polycrystal silicon.
Claim 7
Dependent Claim
20 words
A semiconductor memory device according to claim 1, wherein said conductive member is provided on both sides of said groove.
Claim 8
Dependent Claim
41 words
A semiconductor memory device according to claim 1 wherein said drain/source region is in the main surface of the substrate, the groove extends to a depth into the substrate which is below the depth of the drain/source region of said transistor.
Claim 9
Dependent Claim
189 words
A semiconductor memory device for storing information as a function of the presence or absence of electrical charges stored in a trench capacitor, comprising: a semiconductor substrate having a main surface and a trench formed therein, said trench having a sidewall surface and a bottom wall surface, a transistor formed on said semiconductor substrate, a first impurity diffusion layer formed in the sidewall surface and the bottom wall surface of said trench, a second impurity diffusion layer formed in said main surface of said semiconductor substrate and electrically connecting said first impurity diffusion layer to said transistor, a conductive member provided on said semiconductor substrate and in electrical contact with said second impurity diffusion layer, said conductive member having an opening portion for exposing said trench therethrough, a wall surface defining the opening portion of said conductive member being coplanar with the side wall surface of said trench, and a capacitor insulating film on the side wall surface of said trench and on the wall surface defining the opening portion of said conductive member and covering said conductive member, and a cell plate electrode covering said capacitor insulating film.
Claim 10
Dependent Claim
189 words
A semiconductor memory device for storing information as a function of the presence or absence of electrical charges stored in a trench capacitor, comprising: a semiconductor substrate having a main surface and a trench formed therein, said trench having a sidewall surface and a bottom wall surface, a transistor formed on said semiconductor substrate, a first impurity diffusion layer formed in the sidewall surface and the bottom wall surface of said trench, a second impurity diffusion layer formed in said main surface of said semiconductor substrate and electrically connecting said first impurity diffusion layer to said transistor, a conductive member provided on said semiconductor substrate and in electrical contact with said second impurity diffusion layer, said conductive member having an opening portion for exposing said trench therethrough, a wall surface defining the opening portion of said conductive member being coplanar with the side wall surface of said trench, and a capacitor insulating film on the side wall surface of said trench and on the wall surface defining the opening portion of said conductive member and covering said conductive member, and a cell plate electrode covering said capacitor insulating film.
Claim 11
Dependent Claim
42 words
A semiconductor memory device according to claim 8, wherein said transistor includes source and drain regions formed on said main surface of the semiconductor substrate, and wherein said second impurity diffusion layer is connected to one of said source and drain regions.
Claim 12
Dependent Claim
46 words
A semiconductor memory device according to claim 8, wherein said transistor includes a gate electrode provided on the main surface of said semiconductor substrate with a gate insulating film therebetween, and wherein an edge of said conductive member extends to a position above said gate electrode.
Claim 13
Dependent Claim
45 words
A semiconductor memory device according to claim 8, further comprising an oxide film for separating the elements from one another provide don the main surface of said semiconductor substrate wherein an outer edge of said conductive member extends to a position above said oxide film.
Claim 14
Dependent Claim
15 words
A semiconductor memory device according to claim 8, wherein said conductive member surrounds said trench.
Claim 15
Dependent Claim
15 words
A semiconductor memory device according to claim 8, wherein said conductive member comprises polycrystal silicon.
Claim 16
Dependent Claim
20 words
A semiconductor memory device according to claim 8, wherein said conductive member is provided on both sides of said trench.
Claim 17
Dependent Claim
44 words
A semiconductor memory device according to claim 8 wherein said transistor includes a drain/source region formed in the main surface of the substrate, the trench extends to a depth into the substrate which is below the depth of the drain/source region of said transistor.
Claim 18
Dependent Claim
28 words
A semiconductor memory device as recited in claim 1 wherein said conductive member is on said second impurity diffusion layer in the main surface of said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |