Semiconductor memory device and manufacturing method

Claim 1

A semiconductor memory device for an integrated circuit comprising: a semiconductor substrate (11) of a first conductivity type; groove means extending into the substrate; a field insulation layer (12) on the semiconductor substrate (11); a switch including a gate insulation layer (13), a gate electrode (14) on the gate insulation layer (13), and two impurity regions (15, 16) of a second conductivity type in the substrate (11) adjacent to the gate electrode (14) and a'capacitor, characterised in that the capacitor includes a first electrode (19) connected to one said impurity region (16), a second electrode (21) connectable to a predetermined voltage, insulation means (20) for separating the first and second electrodes (19, 21). and wherein said groove means increases the capacitance area of the first electrode (19).

Claim 10

A method for manufacturing a semiconductor memory device having a semiconductor substrate (11) of a first conductivity type comprising the steps of: (a) forming a field insulation layer (12) on the surface of the semiconductor substrate (11) by selective oxidation; (b) forming a gate insulation layer (13) on the semiconductor substrate (11); (c) depositing a first polycrystalline silicon layer on the gate insulation layer (13) to form a transfer gate electrode (14): (d) diffusing an impurity into the substrate (11) adjacent to the gate insulation layer (13) to form spaced diffusion regions (15, 16) in the substrate (11); characterised by the steps of (e) depositing a thermal oxidation layer on the surface of the substrate (11) and the transfer gate electrode (14); (f) etching a groove (18) through the thermal oxidation layer and into the substrate (11), the groove abutting one of the diffusion regions (15, 16): (g) depositing a second polycrystalline silicon layer for connection to one of the diffusion regions (15, 16): (h) selectively etching the second polycrystalline silicon layer to form a first electrode (19); (i) depositing a capacitor insulation layer (20) over the surface of the first electrode (19): (j) depositing a third polycrystalline silicon layer over the capacitor insulation layer (20) and the groove (18); (k) selectively etching the third polycrystalline layer to form a second electrode (21); (1) depositing a second oxidation layer (22) over the entire substrate (11); (m) etching an opening (24) in the second oxidation layer (22) for exposing the other of the diffusion regions (15, 16); and (n) depositing an aluminum layer (23) over the entire substrate (11) for contacting the other of the diffusion regions (15, 16) through the opening (24).

Claim 11

A method for manufacturing a semiconductor memory device having a semiconductor substrate (11) of a first conductivity type comprising the steps of: (a) forming a field insulation layer (12) on the surface of the semiconductor substrate (11) by selective oxidation; (b) forming a gate insulation layer (13) on the semiconductor substrate (11); (c) depositing a first polycrystalline silicon layer on the gate insulation layer (13) to form a transfer gate electrode (14): (d) diffusing an impurity into the substrate (11) adjacent to the gate insulation layer (13) to form spaced diffusion regions (15, 16) in the substrate (11); characterised by the steps of (e) depositing a thermal oxidation layer on the surface of the substrate (11) and the transfer gate electrode (14); (f) etching a groove (18) through the thermal oxidation layer and into the substrate (11), the groove abutting one of the diffusion regions (15, 16): (g) depositing a second polycrystalline silicon layer for connection to one of the diffusion regions (15, 16): (h) selectively etching the second polycrystalline silicon layer to form a first electrode (19); (i) depositing a capacitor insulation layer (20) over the surface of the first electrode (19): (j) depositing a third polycrystalline silicon layer over the capacitor insulation layer (20) and the groove (18); (k) selectively etching the third polycrystalline layer to form a second electrode (21); (1) depositing a second oxidation layer (22) over the entire substrate (11); (m) etching an opening (24) in the second oxidation layer (22) for exposing the other of the diffusion regions (15, 16); and (n) depositing an aluminum layer (23) over the entire substrate (11) for contacting the other of the diffusion regions (15, 16) through the opening (24).

Claim 12

A method for manufacturing a semiconductor memory device having a semiconductor substrate (11) of a first conductivity type comprising the steps of: (a) forming a field insulation layer (12) on the surface of the semiconductor substrate (11) by selective oxidation; (b) forming a gate insulation layer (13) on the semiconductor substrate (11); (c) depositing a first polycrystalline silicon layer on the gate insulation layer (13) to form a transfer gate electrode (14); (d) diffusing an impurity into the substrate (11) adjacent to the gate insulation layer (13) to form spaced diffusion regions (15, 16) in the substrate (11); characterised by the steps of (e) depositing a first thermal oxidation layer on the surface of the substrate (11) and the transfer gate electrode (14); (f) etching a groove (18) through the first thermal oxidation layer and into the substrate (11) for abutting one of the diffusion regions (15, 16); (g) depositing a second thermal oxidation layer on the surface of the substrate (11); (h) re-etching a part of the groove (18) to leave a part of the second thermal oxidation layer in the groove (18): (i) depositing a second polycrystalline silicon layer for connection to one of the diffusion regions (15, 16); (j) selectively etching the second polycrystalline silicon layer to form a first electrode (19): (k) depositing a capacitor insulation layer (20) over the surface of the first electrode (19); (1) depositing a third polycrystalline silicon layer over the capacitor insulation layer (20) and the groove (18); (m) selectively etching the third polycrystalline layer to form a second electrode (21); (n) depositing a third oxidation layer (22) over the entire substrate (11); (o) etching a hole (24) through the third oxidation layer (22) for exposing the other of the diffusion regions (15, 16); and (p) depositing an aluminium layer (23) over the entire substrate (11) for contacting the other of the diffusion regions (15, 16) through the hole (24).

Claim 13

A method for manufacturing a semiconductor memory device having a semiconductor substrate (11) of a first conductivity type comprising the steps of: (a) forming a field insulation layer (12) on the surface of the semiconductor substrate (11) by selective oxidation; (b) forming a gate insulation layer (13) on the semiconductor substrate (11); (c) depositing a first polycrystalline silicon layer on the gate insulation layer (13) to form a transfer gate electrode (14); (d) diffusing an impurity into the substrate (11) adjacent to the gate insulation layer (13) to form spaced diffusion regions (15, 16) in the substrate (11); characterised by the steps of (e) depositing a first thermal oxidation layer on the surface of the substrate (11) and the transfer gate electrode (14); (f) etching a groove (18) through the first thermal oxidation layer and into the substrate (11) for abutting one of the diffusion regions (15, 16); (g) depositing a second thermal oxidation layer on the surface of the substrate (11); (h) re-etching a part of the groove (18) to leave a part of the second thermal oxidation layer in the groove (18): (i) depositing a second polycrystalline silicon layer for connection to one of the diffusion regions (15, 16); (j) selectively etching the second polycrystalline silicon layer to form a first electrode (19): (k) depositing a capacitor insulation layer (20) over the surface of the first electrode (19); (1) depositing a third polycrystalline silicon layer over the capacitor insulation layer (20) and the groove (18); (m) selectively etching the third polycrystalline layer to form a second electrode (21); (n) depositing a third oxidation layer (22) over the entire substrate (11); (o) etching a hole (24) through the third oxidation layer (22) for exposing the other of the diffusion regions (15, 16); and (p) depositing an aluminium layer (23) over the entire substrate (11) for contacting the other of the diffusion regions (15, 16) through the hole (24).