US4894696A
Expired / Lapsed
US
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Dynamic random access memory having a trench capacitor
Assignee: Hitachi Ltd
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Filing: 1986-12-08
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Granted: 1990-01-16
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Expires: 2006-12-08
Abstract
Abstract A very highly integrated semiconductor memory which enables the dynamic random access memory to develop less soft error and to eliminate margin for aligning the masks, that hinders the device from being highly integrated. The memory cell capacitor is constituted by a trench which is provided at a position defined by an insulator formed on the side of gate electrode of a MOS transistor that constitutes the memory cell. Therefore, the MOS transistor and the trench capacitor are self-aligned, and no margin is required for alignment.
Inventors
- 👤 Eiji Takeda
- 👤 Kiyoo Itoh
- 👤 Ryoichi Hori
- 👤 Katsuhiro Shimohigashi
- 👤 Katsutaka Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:38
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/31; H10B12/37; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
105 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semiconductor body, including a gate electrode and sidewall insulators formed on side surfaces of said gate electrode; and a trench capacitor which is at least partly formed in said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to said sidewall insulator of said gate electrode, said trench capacitor forming the memory capacitor of a transistor memory cell of a dynamic random access memory, and wherein said memory capacitor is provided in the trench and extends over said gate electrode.
Claim 2
Dependent Claim
105 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semiconductor body, including a gate electrode and sidewall insulators formed on side surfaces of said gate electrode; and a trench capacitor which is at least partly formed in said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to said sidewall insulator of said gate electrode, said trench capacitor forming the memory capacitor of a transistor memory cell of a dynamic random access memory, and wherein said memory capacitor is provided in the trench and extends over said gate electrode.
Claim 3
Dependent Claim
106 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semi-conductor body, including a gate electrode and sidewall insulators formed on side surfaces of said gate electrode; a trench capacitor which is at least partly formed in said semiconductor body; and a p-type layer and an n-type layer provided between said trench capacitor and said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to said sidewall insulator of said gate electrode, and said trench capacitor forming the memory capacitor of a transistor memory cell of a dynamic random access memory.
Claim 4
Dependent Claim
106 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semi-conductor body, including a gate electrode and sidewall insulators formed on side surfaces of said gate electrode; a trench capacitor which is at least partly formed in said semiconductor body; and a p-type layer and an n-type layer provided between said trench capacitor and said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to said sidewall insulator of said gate electrode, and said trench capacitor forming the memory capacitor of a transistor memory cell of a dynamic random access memory.
Claim 5
Dependent Claim
103 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semiconductor body, including a gate electrode and sidewall insulators formed on side surfaces of said gate electrode; and a trench capacitor which is at least partly formed in said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to said sidewall insulator of said gate electrode, and said trench capacitor forming the memory capacitor of a transistor memory cell of a dynamic random access memory, and wherein said dynamic random access memory forms a folded bit line structure.
Claim 6
Dependent Claim
103 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semiconductor body, including a gate electrode and sidewall insulators formed on side surfaces of said gate electrode; and a trench capacitor which is at least partly formed in said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to said sidewall insulator of said gate electrode, and said trench capacitor forming the memory capacitor of a transistor memory cell of a dynamic random access memory, and wherein said dynamic random access memory forms a folded bit line structure.
Claim 7
Dependent Claim
164 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semi-conductor body, wherein the field effect transistor includes a gate electrode forming a word line, and source and drain regions; first and second sidewall insulators formed on opposite side surfaces of the gate electrode; a trench capacitor which is at least partly formed in said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to the first sidewall insulator of the gate electrode by using the first sidewall insulator as a mask; a capacitor dielectric layer formed over surfaces of the trench; and a wiring layer connected to the source or drain regions, wherein the wiring layer is a bit line of a dynamic random access memory, wherein said trench capacitor forms the memory capacitor of a transistor memory cell of the dynamic random access memory, and wherein said dynamic random access memory forms a folded bit line structure.
Claim 8
Dependent Claim
164 words
A semiconductor device comprising: a semiconductor body; a field effect transistor provided on the semi-conductor body, wherein the field effect transistor includes a gate electrode forming a word line, and source and drain regions; first and second sidewall insulators formed on opposite side surfaces of the gate electrode; a trench capacitor which is at least partly formed in said semiconductor body, wherein the trench of said trench capacitor is a substantially vertical wall trench and is formed being self-aligned to the first sidewall insulator of the gate electrode by using the first sidewall insulator as a mask; a capacitor dielectric layer formed over surfaces of the trench; and a wiring layer connected to the source or drain regions, wherein the wiring layer is a bit line of a dynamic random access memory, wherein said trench capacitor forms the memory capacitor of a transistor memory cell of the dynamic random access memory, and wherein said dynamic random access memory forms a folded bit line structure.
Claim 9
Dependent Claim
20 words
A semiconductor device according to claim 1, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate.
Claim 10
Dependent Claim
19 words
A semiconductor device according to claim 1, wherein said sidewall insulator has a width of 0.35 μm or less.
Claim 11
Dependent Claim
34 words
A semiconductor device according to claim 1, wherein said sidewall insulator is formed only on said side surfaces of said gate electrode and does not extend on the top surface of said gate electrode.
Claim 12
Dependent Claim
25 words
A semiconductor device according to claim 1, wherein a p-type layer and an n-type layer are provided between said trench capacitor and said semiconductor body.
Claim 13
Dependent Claim
19 words
A semiconductor device according to claim 1, wherein said dynamic random access memory forms a folded bit line structure.
Claim 14
Dependent Claim
20 words
A semiconductor device according to claim 1, wherein said sidewall insulators each have a width of 0.35 μm or less.
Claim 15
Dependent Claim
35 words
A semiconductor device according to claim 1, wherein said sidewall insulators are each formed only on said side surfaces of said gate electrode and do not extend on the top surface of said gate electrode.
Claim 16
Dependent Claim
22 words
A semiconductor device according to claim 2, wherein said memory capacitor is provided in the trench and extends over said gate electrode.
Claim 17
Dependent Claim
20 words
A semiconductor device according to claim 12, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate.
Claim 18
Dependent Claim
19 words
A semiconductor device according to claim 2, wherein said dynamic random access memory forms a folded bit line structure.
Claim 19
Dependent Claim
53 words
A semiconductor device according to claim 4, further comprising a charge storage layer formed on surfaces of the trench, and extending over the gate electrode, wherein the charge storage layer stores information data of the transistor memory cell, and wherein said capacitor dielectric layer is formed on surfaces of said charge storage layer.
Claim 20
Dependent Claim
20 words
A semiconductor device according to claim 4, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate.
Claim 21
Dependent Claim
25 words
A semiconductor device according to claim 4, wherein a p-type layer and an n-type layer are provided between said trench capacitor and said semiconductor body.
Claim 22
Dependent Claim
25 words
A semiconductor device according to claim 16, wherein an impurity concentration of the semiconductor substrate is higher than an impurity concentration of the epitaxial layer.
Claim 23
Dependent Claim
34 words
A semiconductor device according to claim 4, further comprising a device isolation insulating film formed on the semiconductor body, wherein the trench of said trench capacitor is self-aligned to the device isolation insulating film.
Claim 24
Dependent Claim
26 words
A semiconductor device according to claim 4, wherein the wiring layer is self-aligned to the gate electrode by using the second sidewall insulator as a mask.
Claim 25
Dependent Claim
23 words
A semiconductor device according to claim 4, wherein the wiring layer connects to the source or drain region through a polycrystalline silicon layer.
Claim 26
Dependent Claim
34 words
A semiconductor device according to claim 4, wherein the source and drain regions include a lightly doped region and a heavily doped region, and the lightly doped region is formed under a gate dielectric.
Claim 27
Dependent Claim
23 words
A semiconductor device according to claim 4, wherein the capacitor dielectric layer consists of a silicon oxide film and a silicon nitride film.
Claim 28
Dependent Claim
23 words
A semiconductor device according to claim 4, wherein said first and second sidewall insulators each have a width of 0.35 μm or less.
Claim 29
Dependent Claim
38 words
A semiconductor device according to claim 4, wherein said first and second sidewall insulators are each formed only on said side surfaces of said gate electrode and do not extend on the top surface of said gate electrode.
Claim 30
Dependent Claim
22 words
A semiconductor device according to claim 3, wherein said memory capacitor is provided in the trench and extends over said gate electrode.
Claim 31
Dependent Claim
20 words
A semiconductor device according to claim 26, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate.
Claim 32
Dependent Claim
25 words
A semiconductor device according to claim 3, wherein a p-type layer and an n-type layer are provided between said trench capacitor and said semiconductor body.
Claim 33
Dependent Claim
19 words
A semiconductor device according to claim 3, wherein said sidewall insulator has a width of 0.35 μm or less.
Claim 34
Dependent Claim
34 words
A semiconductor device according to claim 3, wherein said sidewall insulator is formed only on said side surfaces of said gate electrode and does not extend on the top surface of said gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |