Semiconductor memory device having trench and stacked polysilicon storage capacitors

Claim 2

In a semiconductor memory comprising an array of transistors formed on a semiconductor substrate of a first conductivity type, wherein each of said transistors has source and drain impurity regions of an opposite conductivity type formed in said substrate and a gate between and insulated from said source and drain impurity regions: a first, trench-type capacitor coupled to a first one of said transistors, said first trench-type capacitor comprising a first impurity region on the sidewall of a trench formed in said substrate and a first conductive material in said trench separated from said first impurity region by an insulating layer, said first impurity region and said first conductive material forming plates of said trench-type capacitor; and a second, stacked capacitor coupled to a second one of said transistors adjacent said first transistor, said second, stacked capacitor comprising a second conductive material insulated from said first conductive material and disposed vertically to and entirely outside said trench, said first and second conductive materials forming plates of said second, stacked capacitor.

Claim 3

A semiconductor memory according to claim 1, wherein said first impurity region is also formed on the bottom surface of said trench.

Claim 4

A semiconductor memory according to claim 1, wherein said first conductive material has a first horizontal portion and said second conductive material has a second horizontal portion.

Claim 5

A semiconductor memory according to claim 3, wherein said second horizontal portion is formed on said first horizontal portion through an insulating film, said first horizontal portion, said second horizontal portion and said insulating film constituting said second, stacked capacitor.

Claim 6

A semiconductor random access memory device formed of an array of memory cells, comprising: a semiconductor substrate of a particular conductivity type and having a main surface, a trench extending from a given portion of the main surface into the substrate; an insulating film formed on the surface of said trench and on the major surface of said substrate; a first impurity region of an opposite conductivity type formed on at least the sidewall of said trench and beneath said film; a first conductive material formed in said trench on said insulating film; said first impurity region and said first conductive material with said insulating film formed therebetween constituting a first, trench-type capacitor for storing electric charge representing information associated with one of said cells; a second impurity region of said opposite conductivity type formed on the major surface on one side of said trench and spaced from said first impurity region; a third impurity region of said opposite conductivity type formed on the major surface of said substrate on an opposite side of said trench and spaced from said first impurity region; a fourth impurity region of said opposite conductivity type formed on the major surface of said substrate on said one side of said trench and spaced from said second impurity region; second conductivity materials in said insulating film between said first and third impurity regions and between said second and fourth impurity regions; a third conductive material in said insulating film in contact with said second impurity region and extending vertically with respect to said first conductive material and insulated therefrom by said insulating film; said first and third conductive materials and said insulating film forming a second, stacked capacitor for storing electric charge representing information associated with a second one of said cells, said third conductive material being disposed above, and entirely outside, said trench; said first and third impurity regions forming the source/drain regions and one of the second conductive materials forming the gate region of a first transistor associated with said trench-type capacitor; and said second and fourth impurity regions forming the source/drain regions and the other one of the second conductive materials forming the gate region of a second transistor associated with said stacked capacitor.

Claim 7

A semiconductor random access memory device formed of an array of memory cells, comprising: a semiconductor substrate of a particular conductivity type and having a main surface, a trench extending from a given portion of the main surface into the substrate; an insulating film formed on the surface of said trench and on the major surface of said substrate; a first impurity region of an opposite conductivity type formed on at least the sidewall of said trench and beneath said film; a first conductive material formed in said trench on said insulating film; said first impurity region and said first conductive material with said insulating film formed therebetween constituting a first, trench-type capacitor for storing electric charge representing information associated with one of said cells; a second impurity region of said opposite conductivity type formed on the major surface on one side of said trench and spaced from said first impurity region; a third impurity region of said opposite conductivity type formed on the major surface of said substrate on an opposite side of said trench and spaced from said first impurity region; a fourth impurity region of said opposite conductivity type formed on the major surface of said substrate on said one side of said trench and spaced from said second impurity region; second conductivity materials in said insulating film between said first and third impurity regions and between said second and fourth impurity regions; a third conductive material in said insulating film in contact with said second impurity region and extending vertically with respect to said first conductive material and insulated therefrom by said insulating film; said first and third conductive materials and said insulating film forming a second, stacked capacitor for storing electric charge representing information associated with a second one of said cells, said third conductive material being disposed above, and entirely outside, said trench; said first and third impurity regions forming the source/drain regions and one of the second conductive materials forming the gate region of a first transistor associated with said trench-type capacitor; and said second and fourth impurity regions forming the source/drain regions and the other one of the second conductive materials forming the gate region of a second transistor associated with said stacked capacitor.

Claim 8

A semiconductor random access memory device according to claim 5, wherein said first conductive material comprises a first vertical portion and a first horizontal portion, said trench being filled with the material of said first vertical portion.

Claim 9

A semiconductor random access memory device according to claim 6, wherein said third conductive material comprises a second vertical portion and a second horizontal portion, said second vertical portion being connected to said second impurity region.

Claim 10

A semiconductor random access memory device according to claim 7, wherein said second horizontal portion is formed on said first horizontal portion with said insulating film formed therebetween, said first horizontal portion, said second horizontal portion and said insulating film constituting said trench-type capacitor.

Claim 11

A semiconductor random access memory device according to claim 8, wherein said first and second horizontal portions are located over said one of said second conductive materials.

Claim 12

A semiconductor random access memory device according to claim 5, wherein said trench-type capacitor and said stacked capacitor have the same charge storage capacitance.

Claim 13

A semiconductor random access memory device according to claim 5, wherein said first and third conductive materials comprise polysilicon.

Claim 14

A semiconductor random access memory device according to claim 5, wherein said semiconductor substrate comprises a silicon substrate.

Claim 15

In a semiconductor memory comprising an array of transistors formed on a semiconductor substrate of a first conductivity type, wherein each of said transistors has source and drain impurity regions of an opposite conductivity type formed in said substrate and a gate between and insulated from said source and drain impurity regions: a first, trench-type capacitor coupled to a first one of said transistors, said first trench-type capacitor comprising a first impurity region on the sidewall of a trench formed in said substrate and a first conductive material in said trench separated from said first impurity region by an insulating layer, said first impurity region and said first conductive material forming plates of said trench-type capacitor; and a second, stacked capacitor coupled to a second one of said transistors adjacent said first transistor, said second, stacked capacitor comprising a second conductive material disposed entirely outside said trench vertically to and insulated from said first conductive material, said first and second conductive materials forming plates of said second, stacked capacitor; wherein said first and second conductive materials have horizontal portions that extend above the gate of one of said transistors.

Claim 16

In a semiconductor memory comprising an array of transistors formed on a semiconductor substrate of a first conductivity type, wherein each of said transistors has source and drain impurity regions of an opposite conductivity type formed in said substrate and a gate between and insulated from said source and drain impurity regions: a first, trench-type capacitor coupled to a first one of said transistors, said first trench-type capacitor comprising a first impurity region on the sidewall of a trench formed in said substrate and a first conductive material in said trench separated from said first impurity region by an insulating layer, said first impurity region and said first conductive material forming plates of said trench-type capacitor; and a second, stacked capacitor coupled to a second one of said transistors adjacent said first transistor, said second, stacked capacitor comprising a second conductive material disposed entirely outside said trench vertically to and insulated from said first conductive material, said first and second conductive materials forming plates of said second, stacked capacitor; wherein said first and second conductive materials have horizontal portions that extend above the gate of one of said transistors.