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JPS627153A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: Hitachi Ltd
•
Filing: 1985-07-03
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Granted: —
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Expires: 2005-07-03
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Abstract

Abstract PURPOSE:To obtain a dynamic MOS.RAM memory cell having high yield by forming a word line of the first gate electrode layer, burying the second and third gate electrode layers in a deep hole to form a storage capacity, and forming a plate electrode of the third gate electrode layer. CONSTITUTION:A transfer transistor of dynamic memory cell is composed of the first gate electrode layer 15, and source and drain diffused layers 16, 17. The first gate electrode layers 15, 18 operate as word line of a memory cell. The second gate electrode 19 layer made of polycrystalline silicon is formed on the surface of a thin insulating film 14 in a deep hole 13, and the electrode of an insulating film capacity is formed of the film 14 to a silicon substrate 1. Further thin insulating film 20 is formed, and the third polycrystalline silicon layer 21 is formed thereon as a plates electrode. The storage capacity is formed of the first insulating film capacity between the substrate 1 and the layer 19, and the second insulating film capacity between the second electrode layer and the third electrode layer.

Inventors

  • 👤 Yoshio Sakai
  • 👤 芳男 酒井
  • 👤 Katsuhiro Shimohigashi
  • 👤 下東 勝博
  • 👤 Toshiaki Masuhara
  • 👤 増原 利明
  • 👤 Osamu Minato
  • 👤 湊 修

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 17:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/377

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