Semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of memory cells provided with a semiconductor substrate of a first conductivity type, each said memory cell including: a groove in said substrate and a first insulation film on the surface of said groove; a transfer gate transistor having a drain region and a source region formed in said substrate with a channel region therebetween, and a gate formed on a gate insulation film on said channel region; and a capacitor including a first conductive layer on said first insulation film, said first conductive layer being electrically coupled to the source region of said transfer gate transistor, a high impurity concentration layer formed in said substrate adjacent said groove, of the same conductivity type as that of said substrate.

Claim 3

A semiconductor memory device according to claim 1, wherein each said capacitor further comprises a second insulation film on said first conductive layer and a second conductive layer on said second insulation film, and a significant part of the capacitance of said capacitor is effectively due to said first and second conductive layers as separated by said second insulation film.

Claim 4

A semiconductor memory device according to claim 1 or 2, wherein said high impurity concentration layer is separately formed for each said memory cell.

Claim 5

A semiconductor memory device according to claim 1 or 2, wherein said high impurity concentration layer is formed in common for respective adjoining ones of said memory cells.

Claim 6

A semiconductor memory device comprising a plurality of memory cells provided with a semiconductor substrate of a first conductivity type, each said memory cell including: a groove in said substrate and a first insulation film on the surface of said groove; a transfer gate transistor having a drain region and a source region formed in said substrate with a channel region therebetween, and a gate formed on a gate insulation film on said channel region; and a capacitor including a first conductive layer on said first insulation film, said first conductive layer being electrically coupled to the source region of said transfer gate transistor, and a second insulation film on said first conductive layer and a second conductive layer on said second insulation film; said semiconductor device further comprising a field oxide on the surface of said substrate between the grooves of respective adjacent ones of said memory cells; wherein both said first and second conductive layers and second insulation film of each said memory cell extend over said gate of said transfer gate transistor of the respective memory cell, each said first insulation layer is thinner than said field oxide, and a significant part of the capacitance of said capacitor is effectively due to said first and second conductive layers as separated by said second insulating film.

Claim 7

A semiconductor memory device comprising a plurality of memory cells provided with a semiconductor substrate of a first conductivity type, each said memory cell including: a groove in said substrate and a first insulation film on the surface of said groove; a transfer gate transistor having a drain region and a source region formed in said substrate with a channel region therebetween, and a gate formed on a gate insulation film on said channel region; and a capacitor including a first conductive layer on said first insulation film, said first conductive layer being electrically coupled to the source region of said transfer gate transistor, and a second insulation film on said first conductive layer and a second conductive layer on said second insulation film; said semiconductor device further comprising a field oxide on the surface of said substrate between the grooves of respective adjacent ones of said memory cells; wherein both said first and second conductive layers and second insulation film of each said memory cell extend over said gate of said transfer gate transistor of the respective memory cell, each said first insulation layer is thinner than said field oxide, and a significant part of the capacitance of said capacitor is effectively due to said first and second conductive layers as separated by said second insulating film.

Claim 8

A semiconductor memory device according to claim 2, wherein said first and second conductive layer and said second insulation film extend over said gate of said transfer gate transistor of the respective memory cell.

Claim 9

A semiconductor memory device comprising a plurality of memory cells provided with a semiconductor substrate of a first conductivity type having a semiconductor layer formed thereon of a conductivity type opposite to said first conductivity type, each said memory cell including: a groove in said semiconductor layer and a first insulation film on the surface of said groove; a transfer gate transistor having a drain region and a source region formed in said semiconductor layer with a channel region therebetween, and a gate formed on a gate insulation film on said channel region; a capacitor including a first conductive layer on said first insulating film, said first conductive layer being electrically coupled to said source region of said transfer gate transistor, and said semiconductor memory device further comprising means for reversely biasing a PN junction formed by said semiconductor layer and said substrate of opposite conductivity types to form a depletion region extending under each said transfer gate transistor and at least a part of said groove of each said memory cell.

Claim 10

A semiconductor memory device comprising a plurality of memory cells provided with a semiconductor substrate of a first conductivity type having a semiconductor layer formed thereon of a conductivity type opposite to said first conductivity type, each said memory cell including: a groove in said semiconductor layer and a first insulation film on the surface of said groove; a transfer gate transistor having a drain region and a source region formed in said semiconductor layer with a channel region therebetween, and a gate formed on a gate insulation film on said channel region; a capacitor including a first conductive layer on said first insulating film, said first conductive layer being electrically coupled to said source region of said transfer gate transistor, and said semiconductor memory device further comprising means for reversely biasing a PN junction formed by said semiconductor layer and said substrate of opposite conductivity types to form a depletion region extending under each said transfer gate transistor and at least a part of said groove of each said memory cell.

Claim 11

A semiconductor memory device according to claim 7, wherein the groove of each said memory cell extends through said semiconductor layer into said semiconductor substrate.

Claim 12

A semiconductor memory device according to claim 7, wherein the groove of each said memory cell terminates within said semiconductor layer, and said depletion region formed along said PN junction as a result of the reverse bias extends to at least a part of said groove.

Claim 13

A semiconductor memory device according to claim 9, wherein said semiconductor layer of said substrate is not present in a respective area between the grooves of respective ajoining ones of said memory cells, in which area said semiconductor substrate of said first conductivity type extends to said first insulation films.

Claim 14

The device of claim 1, 2, 5, 6, 7, 8, 9 or 10, comprising a field oxide on the surface of said substrate, between the grooves of respective adjacent ones of said memory cells.

Claim 15

The device of claim 3, comprising a field oxide on the surface of said substrate, between the grooves and high impurity concentration layers of respective adjacent ones of said memory cells.

Claim 16

The device of claim 4, said first insulation film being the only insulation layer at the surface of said substrate between the grooves of respective adjacent ones of said memory cells.

Claim 17

The device of claim 2, 5, 6, 7, 8, 9 or 10, said second conductive layer extending in common between the grooves of respective adjacent ones of said memory cells.

Claim 18

The semiconductor memory device of claim 5, wherein said second conductive layer extends further onto said gate of said transfer gate transistor than said first conductive layer, and is insulated from said gate.

Claim 19

The semiconductor memory device of claim 1, wherein the capacitance of said capacitor is effectively provided by said high impurity concentration layer and said first conductive layer as separated by said first insulation film.

Claim 20

The semiconductor memory device of claim 7, 8, 9 or 10, each said memory cell comprising a second insulation film on said first conductive layer and a second conductive layer on said second insulation film, wherein the capacitance of each said capacitor is effectively provided by said first and second conductive layers as separated by said second insulation layer.