Patent US5065090A successfully refreshed from Google Patents.
US5065090A
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Method for testing integrated circuits having a grid-based, "cross-check" te
Assignee: Cross-Check Technology Inc
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Filing: 1988-07-13
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Granted: 1991-11-12
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Expires: 2008-07-13
Abstract
Abstract A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured. Conversely, by the excitation of an appropriate probe-line and application of a test signal on another appropriate sense-line the electrical signal on any of the test-points can be externally controlled for the purpose of testing.
Inventors
- 👤 Tushar R. Gheewala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/32; G11C29/48
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
226 words
A method for electrically testing an integrated circuit comprising arbitrary function combinatorial logic gates and an array of electronic switches connected to test-points on said integrated circuit, said electronic switches having access to test-electronics by means of probe-lines and sense-lines, said method comprising the steps of: a. applying test patterns to said integrated circuit from test electronics; b. selectively applying ON signal levels to a selected one probe-line connected to a single row of an array of electronic switches, each electronic switch being a three-terminal memory-less electronic switch having a test terminal, a control terminal and a sense terminal, said test terminal being electrically connected to a first test-point at a logic signal-generating node of one of said arbitrary function combinatorial logic gates in said integrated circuit, said sense terminal being connected to one of said sense-lines, and said control terminal being connected to one of said probe-lines; c. sensing individually through said sense-lines test signals by means of said test terminal of said electronic switch controlled by said selected one probe-line; d. individually measuring with said test electronics said test signals present on selected said sense-lines; e. repeating steps b. through d. for selected rows of said array of said electronic switches; and f. repeating steps a. through e. while applying further test patterns to said integrated circuit until said integrated circuit has been tested.
Claim 2
Independent Claim
226 words
A method for electrically testing an integrated circuit comprising arbitrary function combinatorial logic gates and an array of electronic switches connected to test-points on said integrated circuit, said electronic switches having access to test-electronics by means of probe-lines and sense-lines, said method comprising the steps of: a. applying test patterns to said integrated circuit from test electronics; b. selectively applying ON signal levels to a selected one probe-line connected to a single row of an array of electronic switches, each electronic switch being a three-terminal memory-less electronic switch having a test terminal, a control terminal and a sense terminal, said test terminal being electrically connected to a first test-point at a logic signal-generating node of one of said arbitrary function combinatorial logic gates in said integrated circuit, said sense terminal being connected to one of said sense-lines, and said control terminal being connected to one of said probe-lines; c. sensing individually through said sense-lines test signals by means of said test terminal of said electronic switch controlled by said selected one probe-line; d. individually measuring with said test electronics said test signals present on selected said sense-lines; e. repeating steps b. through d. for selected rows of said array of said electronic switches; and f. repeating steps a. through e. while applying further test patterns to said integrated circuit until said integrated circuit has been tested.
Claim 3
Independent Claim
269 words
A method for electrically testing an integrated circuit comprising arbitrary function combinatorial logic gates and an array of electronic switches connected to test-points on said integrated circuit, said electronic switches having access to test-electronics by means of probe-lines and sense-lines, said method comprising the steps of: a. applying test patterns to said integrated circuit from test electronics; b. selectively applying ON signal levels to a selected one probe-line connected to a single row of an array of electronic switches, each electronic switch having a test terminal, a control terminal and a sense terminal, wherein said electronic switch comprises a Field Effect Transistor (FET) having as said control terminal a gate electrode, as said test terminal a first one of a source electrode and a drain electrode, and as said sense terminal a second one of said source electrode and said drain electrode, said test terminal being electrically connected to a first test-point at a logic signal-generating node of one of said arbitrary function combinatorial logic gates in said integrated circuit, said sense terminal being connected to one of said sense-lines, and said control terminal being connected to one of said probe-lines; c. sensing individually through said sense-lines test signals by means of said test terminal of said electronic switch controlled by said selected one probe-line; d. individually measuring with said test electronics said test signals present on selected said senselines; e. repeating steps b. through d. for selected rows of said array of said electronic switches; and f. repeating steps a. through e. while applying further test patterns to said integrated circuit until said integrated circuit has been tested.
Claim 4
Independent Claim
269 words
A method for electrically testing an integrated circuit comprising arbitrary function combinatorial logic gates and an array of electronic switches connected to test-points on said integrated circuit, said electronic switches having access to test-electronics by means of probe-lines and sense-lines, said method comprising the steps of: a. applying test patterns to said integrated circuit from test electronics; b. selectively applying ON signal levels to a selected one probe-line connected to a single row of an array of electronic switches, each electronic switch having a test terminal, a control terminal and a sense terminal, wherein said electronic switch comprises a Field Effect Transistor (FET) having as said control terminal a gate electrode, as said test terminal a first one of a source electrode and a drain electrode, and as said sense terminal a second one of said source electrode and said drain electrode, said test terminal being electrically connected to a first test-point at a logic signal-generating node of one of said arbitrary function combinatorial logic gates in said integrated circuit, said sense terminal being connected to one of said sense-lines, and said control terminal being connected to one of said probe-lines; c. sensing individually through said sense-lines test signals by means of said test terminal of said electronic switch controlled by said selected one probe-line; d. individually measuring with said test electronics said test signals present on selected said senselines; e. repeating steps b. through d. for selected rows of said array of said electronic switches; and f. repeating steps a. through e. while applying further test patterns to said integrated circuit until said integrated circuit has been tested.
Claim 5
Dependent Claim
63 words
The method according to claim 2 wherein said gate electrode is coupled to said probe line, and a first one of said source electrode and said drain electrode is connected to one of said sense-lines and a second one of said source electrode and said drain electrode is connected to said test-point, such that said gate electrode is never connected to a test-point.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |